OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC100EP105FAG

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1 Publication Order Number:
MC10EP105/D
MC10EP105, MC100EP105
3.3V / 5VECL Quad 2−Input
Differential AND/NAND
Description
The MC10/100EP105 is a quad 2−input differential AND/NAND
gate. Each gate is functionally equivalent to the EP05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP105 is ideal for applications requiring the fastest AC
performance available.
The 100 Series contains temperature compensation.
Features
• 275 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
MCxxx
EP105
AWLYYWWG
xxx = 10 or 100
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
QFN32
MN SUFFIX
CASE 488AM
32
1
MCxxx
EP105
AWLYYWWG
G
1
(Note: Microdot may be in either location)
MC10EP105, MC100EP105
http://onsemi.com
2
NC
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MC10EP105
MC100EP105
V
EE
D3b
D3b
V
CC
D3a
D3a
D2b
V
CC
V
CC
Q0
Q0
V
EE
D0a
D0a
D0b
V
CC
Q3Q3Q2Q2Q1V
CC
D2bD2aD2aD1bD1bD1aD0b D1a
Figure 1. 32−Lead LQFP Pinout (Top View)
Q1
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
PIN
Dna*, Dnb*, Dna*, Dnb*
Qn, Qn ECL Data Outputs
FUNCTION
ECL Data Inputs
LLHHLH
L HHL L H
H LLH LH
HHLL HL
Table 2. TRUTH TABLE
NC
V
CC
Positive Supply
No Connect
V
EE
Negative Supply
Figure 2. 32−Lead QFN Pinout (Top View)
D0a
D0a
D0b
D0b
Q0
Q0
D1a
D1a
D1b
D1b
Q1
Q1
D2a
D2a
D2b
D2b
Q2
Q2
D3a
D3a
D3b
D3b
Q3
Q3
V
EE
* Pins will default LOW when left open.
Dna Dnb Dna Dnb Qn Qn
Figure 3. Logic Diagram
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
12345 678
24 23 22 21 20 19 18 17
Exposed Pad (EP)
NC
V
EE
D3b
D3b
V
CC
D3a
D3a
D2b
V
CC
V
CC
Q0
Q0
V
EE
D0a
D0a
D0b
V
CC
Q3Q3Q2Q2Q1V
CC
Q1
D2bD2aD2aD1bD1bD1aD0b D1a
MC10EP105, MC100EP105
http://onsemi.com
3
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
LQFP−32
QFN−32
Level 2
−
Level 2
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in
Transistor Count 444 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6
−6
V
I
out
Output Current Continuous
Surge
50
100
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
32 QFN
32 QFN
31
27
°C/W
q
JC
Thermal Resistance (Junction−to−Case) 2S2P 32 QFN 12 °C/W
T
sol
Wave Solder Pb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
P1-P3P4-P6P7-P9P10-P11

MC100EP105FAG

Mfr. #:
Buy MC100EP105FAG
Manufacturer:
ON Semiconductor
Description:
Logic Gates 3.3V/5V ECL Quad 2-Input AND/NAND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet