MC100EP105FAG

MC10EP105, MC100EP105
http://onsemi.com
7
Table 10. 100EP DC CHARACTERISTICS, NECL V
CC
= 0 V, V
EE
= 5.5 V to 3.0 V (Note 17)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current V
CC
= 3.3 V
V
CC
= 5.0 V
45
45
59
63
80
80
45
45
62
66
85
85
45
45
65
69
85
85
mA
V
OH
Output HIGH Voltage (Note 18) 1145 1020 895 1145 1020 895 1145 1020 895 mV
V
OL
Output LOW Voltage (Note 18) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mV
V
IH
Input HIGH Voltage (SingleEnded) 1225 880 1225 880 1225 880 mV
V
IL
Input LOW Voltage (SingleEnded) 1945 1625 1945 1625 1945 1625 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
EE
+2.0 0.0 V
EE
+2.0 0.0 V
EE
+2.0 0.0 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
CC
.
18.All loading with 50 W to V
CC
2.0 V.
19.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS V
CC
= 0 V; V
EE
= 3.0 V to 5.5 V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 20)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
Maximum Frequency
(See Figure 4 F
max
/JITTER)
> 3 > 3 > 3 GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
175 250 325 200 275 350 225 300 375 ps
t
SKEW
Within Device Skew
Device to Device Skew (Note 21)
10 50 10 50 15 50 ps
t
JITTER
CycletoCycle Jitter
(See Figure 4 F
max
/JITTER)
0.2 < 1 0.2 < 1 0.2 < 1 ps
V
PP
Input Voltage Swing
(Differential Configuration)
150 800 1200 150 800 1200 150 800 1200 mV
t
r
t
f
Output Rise/Fall Times Q
(20% 80%)
100 150 200 120 170 220 150 200 250 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V
CC
2.0 V.
21.Skew is measured between outputs under identical transitions.
MC10EP105, MC100EP105
http://onsemi.com
8
0
100
200
300
400
500
600
700
800
900
1000
0 1000 2000 3000 4000 5000
Figure 4. F
max
/Jitter
FREQUENCY (MHz)
1
2
3
4
5
6
7
8
9
10
(JITTER)
V
OUTpp
(mV)
JITTER
OUT
ps (RMS)
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
2.0 V
MC10EP105, MC100EP105
http://onsemi.com
9
ORDERING INFORMATION
Device Package Shipping
MC10EP105FA LQFP32 250 Units / Tray
MC10EP105FAG LQFP32
(PbFree)
250 Units / Tray
MC10EP105FAR2 LQFP32 2000 / Tape & Reel
MC10EP105FAR2G LQFP32
(PbFree)
2000 / Tape & Reel
MC100EP105FA LQFP32 250 Units / Tray
MC100EP105FAG LQFP32
(PbFree)
250 Units / Tray
MC100EP105FAR2 LQFP32 2000 / Tape & Reel
MC100EP105FAR2G LQFP32
(PbFree)
2000 / Tape & Reel
MC10EP105MNG
QFN32
(PbFree)
74 Units / Rail
MC100EP105MNG 74 Units / Rail
MC10EP105MNR4G 1000 / Tape & Reel
MC100EP105MNR4G 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices

MC100EP105FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates 3.3V/5V ECL Quad 2-Input AND/NAND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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