A3916GESTR-T

Dual DMOS Full-Bridge Motor Driver
A3916
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION
Device Operation
The A3916 is a dual full-bridge motor driver capable of operat-
ing one stepper motor, two DC motors, or one high-current DC
motor. MOSFET output stages substantially reduce the voltage
drop and the power dissipation of the A3916 outputs, compared
to typical drivers with bipolar transistors.
Output current can be regulated by pulse-width modulating
(PWM) the inputs. In addition to supporting external PWM of the
driver, the A3916 limits the peak current by internally PWMing
the source driver when the current in the winding exceeds the
peak current, as determined by a sense resistor. If internal current
limiting is not needed, the sense pin should be shorted to ground.
Internal circuit protection includes thermal shutdown with hys-
teresis, undervoltage lockout, internal clamp diodes, crossover
current protection, and overcurrent protection.
External PWM
Output current regulation can be achieved by pulse-width modu-
lating the inputs. Slow decay mode is selected by holding one
input high while PWMing the other input. Holding one input low
and PWMing the other input results in fast decay.
Blanking
This function blanks the output of the current sense comparator
when the outputs are switched. The comparator output is blanked
to prevent false overcurrent detections due to reverse recovery
currents of the clamp diodes or to switching transients related to
the capacitance of the load. The blank time, t
BLANK
, is approxi-
mately 3 μs.
Sleep Mode
An active-low control input used to minimize power consump-
tion when the A3916 is not in use. This disables much of the
internal circuitry including the output drivers, internal regulator,
and charge pump. A logic high allows normal operation. When
coming out of sleep mode, wait 1.5 ms before issuing a command
to allow the internal regulator and charge pump to stabilize.
Enable
When all logic inputs are pulled to logic low, the outputs of the
bridges are disabled. The charge pump and internal circuitry
continue to run when the outputs are disabled.
Thermal Shutdown
The A3916 will disable the outputs if the junction temperature
reaches 165°C. When the junction temperature drops 20°C, the
outputs will be enabled.
Brake Mode
When driving DC motors, the A3916 goes into brake mode (turns
on both sink drivers) when both of its inputs are high (IN1 and
IN2, or IN3 and IN4). There is no current limiting during brak-
ing, so care must be taken to ensure that the peak current during
braking does not exceed the absolute maximum current.
Internal PWM Current Control
Each full-bridge is controlled by a fixed off-time PWM current
control circuit that limits the load current to a desired value, I
TRIP
.
Initially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and the
current sense resistor, R
SENSEx
. When the voltage across R
SENSEx
equals the internal reference voltage, the current sense compara-
tor resets the PWM latch, which turns off the source driver.
The maximum value of current limiting, I
TRIP(max)
, is set by the
selection of the sense resistor, R
SENSEx
, and is approximated by a
transconductance function:
I
TRIP(max)
= 0.2 ÷ R
SENSEx
It is critical to ensure the maximum rating on SENSEx pins
(0.5 V) is not exceeded.
Synchronous Rectification
When a PWM off-cycle is triggered by an internal fixed off-time
cycle, load current recirculates in slow decay SR mode. During
slow decay, current recirculates through the sink-side FET and
the sink-side body diode. The SR feature enables the sink-side
FET, effectively shorting out the body diode. The sink driver is
Dual DMOS Full-Bridge Motor Driver
A3916
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
not enabled until the source driver is turned off and the cross-
over delay has expired. This feature helps lower the voltage drop
during current recirculation, lowering power dissipation in the
bridge.
OCP
If an overcurrent event occurs, both motor bridges are disabled
until either SLEEPn is brought low or the VBB supply is cycled.
FAULTn
This is an open-drain output that is pulled low during a TSD
or overcurrent event. The output is released when the die tem-
perature falls below the TSD level minus the hysteresis. For an
over-current event, the output is held low until either SLEEPn is
brought low or the VBB supply is cycled.
Parallel Operation
The A3916 can be paralleled for applications that require higher
output currents. In paralleled mode, the driver can source 1.8 A
continuous. The A3916 has two completely independent bridges
with separate overcurrent latches. This allows the device to
supply two separate loads, and as a result, when paralleled, it is
imperative that the internal current control is disabled by shorting
the sense pins to ground.
Because the overcurrent trip threshold is internally fixed at 0.2 V,
the trace resistance must be kept small so the internal current
latch is not triggered prematurely. With acceptable margin, the
voltage drop across the trace resistance should be under 0.1 V. At
a peak current of 2.5 A, the trace resistance should be kept below
40 mΩ to prevent false tripping of the overcurrent latch.
Each bridge has some variation in propagation delay. During this
time, it is possible that one bridge will have to support the full
load current for a very short period of time. Propagation delays
are characterized and guard banded to protect the driver from
damage during these events.
Dual DMOS Full-Bridge Motor Driver
A3916
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PACKAGE OUTLINE DRAWINGS
Figure 2: 16-contact 3 mm × 3 mm QFN package (Sufx ES)
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-220WEED-4)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
A
B
C
16
2
1
A
16
1
2
B
1.70
1.70
1.70
1.70
0.30
1
16
3
3
0.75
0.25
0.50
0.40
0.50
0.90
3.1
0
3.10
C
Reference land pattern layout (reference IPC7351 QFN50P300X300X80-17W2M); all pads a minimum
of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and
PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad
land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Terminal #1 mark area
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)

A3916GESTR-T

Mfr. #:
Manufacturer:
Description:
IC MTR DRV BIPOLAR 2.7-15V 16QFN
Lifecycle:
New from this manufacturer.
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