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ZL40220LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Figure 10 - HCSL Input AC Coupled
VDD_driver
VDD_driver
VDD
ZL40220
clk_p
clk_n
CMOS
Driver
R
R
C
Vref = VDD_driver/2
R= 10 K ohms, C = 100 nF
Figure 11 - CMOS Input DC Coupled Referenced to VDD/2
ZL40220 Data Sheet
10
Microsemi Corporation
VDD
VDD_driver
VDD
ZL40220
clk_p
clk_n
CMOS
Driver
R2
C
RA
R3
R1
Figure 12 - CMOS Input DC Coupled Referenced to Ground
Table 2 - Component Values for Single Ended Input Reference to Ground
VDD_driver R1 (kΩ) R2 (kΩ) R3 (kΩ) RA (kΩ) C (pF)
1.5 1.25 3.075 open 10 10
1.8 1 3.8 open 10 10
2.5 0.33 4.2 open 10 10
3.3 0.75 open 4.2 10 10
ZL40220 Data Sheet
11
Microsemi Corporation
* For frequencies below 100 MHz, increase C to avoid signal integrity issues.
ZL40220 Data Sheet
12
Microsemi Corporation
3.3 Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 13.
VDD
3 mA
Output
-
+
+
-
Figure 13 - Simplified LVDS Output Driver
The methods to terminate the
ZL40220 drivers are shown in the following figures.
LVDS
Receiver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40220
clk_p
clk_n
VDD_Rx
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

ZL40220LDG1

Mfr. #:
Buy ZL40220LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 2:6 LVDS Fanout Buffer w/Ext. Term.
Lifecycle:
New from this manufacturer.
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