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ATTINY2313-20SU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
7
2543MS–AVR–10/16
ATtiny2313
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F (0x5F) SREG I T H S V N Z C 8
0x3E (0x5E) Reserved – – – – – – – –
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11
0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 77
0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – –60
0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – –61
0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 78, 109
0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 78
0x37 (0x57) SPMCSR –
–
– CTPB RFLB PGWRT PGERS SELFPRGEN 155
0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 77
0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 53
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 37
0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 76
0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 77
0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 26
0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0
– –WGM01WGM00 73
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1BO
– – WGM11 WGM10 104
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 107
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 108
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 108
0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 108
0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 108
0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 109
0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 109
0x27 (0x47) Reserved – – – – – – – –
0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 28
0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 109
0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 109
0x23 (0x43) GTCCR – – – – – – – PSR10 81
0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 108
0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 42
0x20 (0x40) PCMSK PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 61
0x1F (0x3F) Reserved – – – – – – – –
0x1E (0x3E) EEAR – EEPROM Address Register 16
0x1D (0x3D) EEDR EEPROM Data Register 17
0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 17
0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 58
0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 58
0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 58
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 58
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 58
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 58
0x15 (0x35) GPIOR2 General Purpose I/O Register 2 21
0x14 (0x34) GPIOR1 General Purpose I/O Register 1 21
0x13 (0x33) GPIOR0 General Purpose I/O Register 0 21
0x12 (0x32) PORTD
– PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 58
0x11 (0x31) DDRD
– DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 58
0x10 (0x30) PIND
– PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 58
0x0F (0x2F) USIDR USI Data Register 144
0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 145
0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 145
0x0C (0x2C) UDR UART Data Register (8-bit) 129
0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 129
0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 131
0x09 (0x29) UBRRL
UBRRH[7:0]
133
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 149
0x07 (0x27) Reserved – – – – – – – –
0x06 (0x26) Reserved – – – – – – – –
0x05 (0x25) Reserved
– – – – – – – –
0x04 (0x24) Reserved – – – – – – – –
0x03 (0x23) UCSRC
– UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 132
0x02 (0x22) UBRRH
– – – –
UBRRH[11:8]
133
0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 150
0x00 (0x20) Reserved
– – – – – – – –
8
2543MS–AVR–10/16
ATtiny2313
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
9
2543MS–AVR–10/16
ATtiny2313
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1
COM Rd One’s Complement Rd 0xFF Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd 0x00 Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1
INC Rd Increment Rd Rd + 1 Z,N,V 1
DEC Rd Decrement Rd Rd 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1
CLR Rd Clear Register Rd Rd Rd Z,N,V 1
SER Rd Set Register Rd 0xFF None 1
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC Z None 2
RCALL k Relative Subroutine Call PC PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ZNone3
RET Subroutine Return PC STACK None 4
RETI Interrupt Return PC STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) 1None2
CBI P,b Clear Bit in I/O Register I/O(P,b) 0None2
LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0)
0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ATTINY2313-20SU

Mfr. #:
Buy ATTINY2313-20SU
Manufacturer:
Microchip Technology / Atmel
Description:
8-bit Microcontrollers - MCU 2kB Flash 0.128kB EEPROM 18 I/O Pins
Lifecycle:
New from this manufacturer.
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