April 1995 2
Philips Semiconductors Product specification
N-channel vertical D-MOS transistor BST72A
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in TO-92
variant envelope and designed for
use in telephone ringer circuits and
for application with relay, high-speed
and line-transformer drivers.
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No second breakdown
QUICK REFERENCE DATA
PINNING - TO-92 VARIANT
Drain-source voltage V
DS
max. 80 V
Drain-source voltage (non-repetitive
peak; t
p
≤ 2 ms)
V
DS(SM)
max. 100 V
Gate-source voltage (open drain) V
GSO
max. 20 V
Drain current (DC) I
D
max. 300 mA
Total power dissipation up to
T
amb
=25°C
P
tot
max. 0.83 W
Drain-source ON-resistance
typ.
max.
7
10
Ω
Ω
I
D
= 150 mA; V
GS
=5 V R
DS(on)
Transfer admittance
I
D
= 200 mA; V
DS
=5 V Y
fs
typ. 150 mS
1 = source
2 = gate
3 = drain
PIN CONFIGURATION
Fig.1 Simplified outline and symbol.
Note: Various pinout configurations available.
handbook, halfpage
1
3
2
MAM146
s
d
g
