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74HCT174D-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
74HC_HCT174_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 17 April 2013 6 of 16
NXP Semiconductors
74HC174-Q100; 74HCT174-Q100
Hex D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristics
C
I
input
capacitance
-3.5-- - - - pF
74HCT174-Q100
V
IH
HIGH-level
input voltage
V
CC
= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20 A 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20 A; V
CC
= 4.5 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 5.2 mA; V
CC
= 5.5 V - 0.15 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
=5.5V
--0.1 - 1- 1 A
I
CC
supply current V
I
= V
CC
or GND; I
O
=0A;
V
CC
=5.5V
--8.0- 80 - 160A
I
CC
additional
supply current
per input pin;
V
I
=V
CC
2.1 V;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
Dn input - 25 90 - 112.5 - 122.5 A
CP input - 130 468 - 585 - 637 A
MR
input - 125 450 - 562.5 - 612.5 A
C
I
input
capacitance
-3.5-- - - - pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC174-Q100
t
pd
propagation
delay
CP to Qn; see Figure 6
[1]
V
CC
= 2.0 V - 55 165 - 205 - 250 ns
V
CC
= 4.5 V - 20 33 - 41 - 50 ns
V
CC
= 5.0 V; C
L
=15pF-17---- - ns
V
CC
= 6.0 V - 16 28 - 35 - 43 ns
74HC_HCT174_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 17 April 2013 7 of 16
NXP Semiconductors
74HC174-Q100; 74HCT174-Q100
Hex D-type flip-flop with reset; positive-edge trigger
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 7
V
CC
= 2.0 V - 44 150 - 190 - 225 ns
V
CC
= 4.5 V - 16 30 - 38 - 45 ns
V
CC
= 5.0 V; C
L
=15pF-13---- - ns
V
CC
= 6.0 V - 13 26 - 33 - 38 ns
t
t
transition time Qn output; see Figure 6
[2]
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
V
CC
= 6.0 V - 6 13 - 16 - 19 ns
t
W
pulse width CP input HIGH or LOW;
see Figure 6
V
CC
= 2.0 V 80 17 - 100 - 120 - ns
V
CC
= 4.5 V 16 6 - 20 - 24 - ns
V
CC
= 6.0 V 14 5 - 17 - 20 - ns
MR
input LOW;
see Figure 7
V
CC
= 2.0 V 80 12 - 100 - 120 - ns
V
CC
= 4.5 V 16 4 - 20 - 24 - ns
V
CC
= 6.0 V 14 3 - 17 - 20 - ns
t
rec
recovery time MR to CP; see Figure 7
V
CC
= 2.0 V +5 11 - +5 - +5 - ns
V
CC
= 4.5 V +5 4- +5 - +5 - ns
V
CC
= 6.0 V +5 3- +5 - +5 - ns
t
su
set-up time Dn to CP; see Figure 6
V
CC
= 2.0 V 60 6 - 75 - 90 - ns
V
CC
= 4.5 V 12 2 - 15 - 18 - ns
V
CC
= 6.0 V 10 2 - 13 - 15 - ns
t
h
hold time Dn to CP; see Figure 6
V
CC
= 2.0 V +3 6- +3 - +3 - ns
V
CC
= 4.5 V +3 2- +3 - +3 - ns
V
CC
= 6.0 V +3 2- +3 - +3 - ns
f
max
maximum
frequency
CP input; see Figure 6
V
CC
= 2.0 V 6 30 - 5 - 4 - MHz
V
CC
= 4.5 V 30 90 - 24 - 20 - MHz
V
CC
= 6.0 V 35 107 - 28 - 24 - MHz
V
CC
= 5.0 V; C
L
=15pF-99---- - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
[3]
-17---- - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT174_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 17 April 2013 8 of 16
NXP Semiconductors
74HC174-Q100; 74HCT174-Q100
Hex D-type flip-flop with reset; positive-edge trigger
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
74HCT174-Q100
t
pd
propagation
delay
CP to Qn; see Figure 6
[1]
V
CC
= 4.5 V - 21 35 - 44 - 53 ns
V
CC
= 5.0 V; C
L
=15pF-18---- - ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 7
V
CC
= 4.5 V - 20 35 - 44 - 53 ns
V
CC
= 5.0 V; C
L
=15pF-17---- - ns
t
t
transition time Qn output; see Figure 6
[2]
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width CP input; see Figure 6
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
MR
input LOW;
see Figure 7
V
CC
= 4.5 V 20 7 - 25 - 30 - ns
t
rec
recovery time MR to CP; see Figure 7
V
CC
= 4.5 V 12 3 - 15 - 18 - ns
t
su
set-up time Dn to CP; see Figure 6
V
CC
= 4.5 V 16 4 - 20 - 24 - ns
t
h
hold time Dn to CP; see Figure 6
V
CC
= 4.5 V 5 3- 5 - 5 - ns
f
max
maximum
frequency
CP input; see Figure 6
V
CC
= 4.5 V 30 63 - 24 - 20 - MHz
V
CC
= 5.0 V; C
L
=15pF-69---- - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-17---- - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

74HCT174D-Q100J

Mfr. #:
Buy 74HCT174D-Q100J
Manufacturer:
Nexperia
Description:
Flip Flops 74HCT174D-Q100/SO16/REEL 13" Q
Lifecycle:
New from this manufacturer.
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