AUIRS2092STR Datasheet AUIRS2092STR, AUIRS2092S | P7-P9

AUIRS2092S

7

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions below. The Vs and COM offset ratings are

tested with supplies biased at V

AA

-V

SS

=10 V, V

CC

=12 V and V

B

-V

S

=12 V. All voltage parameters are absolute voltages referenced

to COM; all currents are defined positive into any lead.

Symbol Definition Min. Max. Units

V

B

High side floating supply absolute voltage V

S

+10 V

S

+18

V

S

High side floating supply offset voltage

(Note 1)

200

V

I

AAZ

Floating input positive supply zener clamp current 1 11

I

SSZ

Floating input negative supply zener clamp current 1 11

mA

V

SS

Floating input supply absolute voltage 0 200

V

HO

High side floating output voltage Vs V

B

V

CC

Low side fixed supply voltage 10 18

V

LO

Low side output voltage 0 V

CC

V

GND

GND pin input voltage V

SS

(Note 3) V

AA

(Note 3)

V

IN-

Inverting input voltage V

GND

-0.5 V

GND

+0.5

V

CSD

CSD pin input voltage V

SS

V

AA

V

COMP

pin input voltage V

SS

V

AA

V

C

COMP

COMP pin phase compensation capacitor to GND 1 - nF

V

DT

DT pin input voltage 0 V

CC

V

I

OREF

Reference output current to COM (Note 2) 0.3 0.8 mA

V

OCSET

pin input voltage 0.5 5

V

CSH

pin input voltage Vs V

B

V

dVss/dt Allowable Vss voltage slew rate upon power-up (Note4) - 50 V/ms

I

PW

Input pulse width 10 (Note 5) - ns

f

SW

Switching Frequency - 800 kHz

T

A

Ambient Temperature -40 125

°C

Note 1:

Logic operational for Vs equal to –5 V to +200 V. Logic state held for Vs equal to –5 V to –V

BS

.

Note 2: Nominal voltage for V

REF

is 5.1 V. I

OREF

of 0.3 – 0.8 mA dictates total external resistor value on VREF to be 6.3 k to

16.7 k.

Note 3: GND input voltage is limited by I

AAZ

and I

SSZ

.

Note 4: V

SS

ramps up from 0 V to 200 V.

Note 5: Output logic status may not respond correctly if input pulse width is smaller than the minimum pulse width.

AUIRS2092S

8

Electrical Characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C  Tj 

125°C with bias conditions of V

CC

,V

BS

= 12 V, V

SS

=V

S

=COM=0 V, V

AA

=10 V, C

L

=1 nF.

Symbol

Definition Min Typ Max Units Test Conditions

Low Side Supply

UV

CC+

Vcc supply UVLO positive threshold 8.4 8.9 9.8

UV

CC-

Vcc supply UVLO negative threshold 8.2 8.7 9.4

UV

CCHYS

UV

CC

hysteresis - 0.2 -

V

I

QCC

Low side quiescent current - - 3 mA V

DT

=V

CC

V

CLAMPL

Low side zener diode clamp voltage 19.6 20.4 21.6 V I

CC

=5 mA

High Side Floating Supply

UV

BS+

High side well UVLO positive threshold 8.0 8.5 9.7

UV

BS-

High side well UVLO negative threshold 7.8 8.3 9.0

UV

BSHYS

UV

BS

hysteresis - 0.2 -

V

I

QBS

High side quiescent current - - 1 mA

I

LKH

High to Low side leakage current - - 50 µA V

B

=V

S

=200 V

V

CLAMPH

High side zener diode clamp voltage 19.6 20.4 21.6 V I

BS

=5 mA

Floating Input Supply

UV

AA+

VA+, VA- floating supply UVLO positive

threshold from V

SS

8.2 8.7 9.7

V

SS

=0 V, GND pin

floating

UV

AA-

VA+, VA- floating supply UVLO negative

threshold from V

SS

7.7 8.2 9.0

V

SS

=0 V, GND pin

floating

UV

AAHYS

UV

AA

hysteresis - 0.5 -

V

SS

=0 V, GND pin

floating

I

QAA0

Floating Input positive quiescent supply

current

- 0.5 2

V

AA

=10 V, V

SS

=0 V,

V

CSD

=VSS

- 6.5 11

V

AA

=10 V, V

SS

=0 V,

V

CSD

=VAA, Tj = -

40C

- 8 11

V

AA

=10 V, V

SS

=0 V,

V

CSD

=VAA, Tj =

25C

I

QAA1

Floating Input positive quiescent supply

current

- 9.5 12.5

V

AA

=10 V, V

SS

=0 V,

V

CSD

=VAA, Tj =

125C

- 6.5 11

mA

V

AA

=10 V, V

SS

=0 V,

V

CSD

=GND, Tj = -

40C

- 8 11

V

AA

=10 V, V

SS

=0 V,

V

CSD

=GND, Tj =

25C

I

QAA2

Floating Input positive quiescent supply

current

- 9.5 12.5

V

AA

=10 V, V

SS

=0 V,

V

CSD

=GND, Tj =

125C

I

LKM

Floating input side to Low side leakage

current

- - 50 µA

V

AA

=V

SS

=V

GND

=

100 V

V

CLAMPM+

V

AA

floating supply zener diode clamp

voltage, positive, with respect to GND

6.0 7.0 8.0

I

AA

=5 mA, I

SS

=5 mA,

V

GND

=0 V,

V

CSD

=VSS

V

CLAMPM-

V

SS

floating supply zener diode clamp

voltage, negative, with respect to GND

-8.0 -7.0 -6.0

V

I

AA

=5 mA, I

SS

=5 mA,

V

GND

=0 V,

V

CSD

=VSS

Audio Input (V

GND

=0, V

AA

=5V, V

SS

=-5V)

-20 0 20 mV Tj = -40C

-15 0 15 mV Tj = 25C

V

OS

Input offset voltage

-18 0 18 mV Tj = 125C

I

BIN

Input bias current - - 40 nA

AUIRS2092S

9

BW Small signal bandwidth - 9 - MHz

C

COMP

=2 nF,

Rf=3.3 k

V

COMP

OTA Output voltage VAA-1 - VSS+1 V

g

m

OTA transconductance - 100 - mS V

IN-

=10 mV

G

V

OTA gain 60 - - dB

V

Nrms

OTA input noise voltage - 250 - mVrms

BW=20 kHz,

Resolution

BW=22 Hz

Fig.5

SR Slew rate - ±5 - V/us C

COMP

=1 nF

CMRR Common-mode rejection ratio - 60 -

PSRR Supply voltage rejection ratio - 65 -

dB

PWM comparator

Vth

PWM

PWM comparator threshold in COMP - (V

AA

-V

SS

)/2 - V

f

OTA

COMP pin star-up local oscillation

frequency

0.7 1.0 1.3 MHz V

CSD

=GND

Protection

V

REF

Reference output voltage 4.8 5.1 5.5 I

OREF

=0.5 mA

Vth

OCL

Low side OC threshold in Vs 1.1 1.2 1.3

OCSET=1.2 V,

Fig.6

Vth

OCH

High side OC threshold in V

CSH

1.1+ Vs 1.2+ Vs 1.3+ Vs Vs=200 V,

Vth1 CSD pin shutdown release threshold 0.62xV

DD

0.70xV

DD

0.78xV

DD

Vth2 CSD pin self reset threshold 0.26xV

DD

0.30xV

DD

0.34xV

DD

V

I

CSD+

CSD pin discharge current 60 100 150 V

CSD

= V

SS

+5 V

I

CSD-

CSD pin charge current 60 100 150

µA

V

CSD

= V

SS

+5 V

t

SD

Shutdown propagation delay from V

CSD

>

V

SS

+ Vth

OCH

to Shutdown

- - 250

t

OCH

Propagation delay time from V

CSH

>

Vth

OCH

to Shutdown

- - 650 Fig.3

t

OCL

Propagation delay time from Vs> Vth

OCL

to Shutdown

- - 650

ns

Fig.4

Gate Driver

Io+ Output high short circuit current (Source) - 1.0 - A Vo=0 V, PW<10 µs

Io- Output low short circuit current (Sink) - 1.2 - A Vo=12 V, PW<10 µs

V

OL

Low level out put voltage

LO – COM, HO - VS

- - 0.1

V

OH

High level out put voltage

VCC – LO, VB - HO

- - 2.3

V Io=2 mA

ton

High and low side turn-on propagation

delay

- 360 -

V

DT

= V

CC

toff

High and low side turn-off propagation

delay

- 335 -

V

DT

= V

CC

tr Turn-on rise time - 20 50

tf Turn-off fall time - 15 35

5 20 35

V

DT

>V

DT1,

Tj = -40C

15 25 35

V

DT

>V

DT1,

Tj = 25C

DT1

Deadtime: LO turn-off to HO turn-on

(DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO

)

20 35 50

V

DT

>V

DT1,

Tj = 125C

20 35 55

V

DT1

>V

DT

> V

DT2,

Tj = -40C

25 40 55

V

DT1

>V

DT

> V

DT2,

Tj = 25C

DT2

Deadtime: LO turn-off to HO turn-on

(DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO

)

30 50 70

V

DT1

>V

DT

> V

DT2,

Tj = 125C

40 65 95

V

DT2

>V

DT

> V

DT3,

Tj = -40C

DT3

Deadtime: LO turn-off to HO turn-on

(DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO

)

50 65 85

ns

V

DT2

>V

DT

> V

DT3,

Tj = 25C

AUIRS2092STR

AUIRS2092STR

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