1N6379RL4

1N6373 - 1N6381 Series (ICTE-5 - ICTE-36)
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4
Figure 6. Dynamic Impedance
1000
500
200
100
50
20
10
5
2
1
0.3 0.5 0.7 1 2 3 5 7 10 20 30
DV
BR
, INSTANTANEOUS INCREASE IN V
BR
ABOVE V
BR(NOM)
(VOLTS)
I
T
, TEST CURRENT (AMPS)
V
BR(MIN)
=6.0 to 11.7V
T
L
=25°C
t
P
=10ms
19V
21.2V
42.4V
Figure 7. Typical Derating Factor for Duty Cycle
DERATING FACTOR
1 ms
10 ms
1
0.7
0.5
0.3
0.05
0.1
0.2
0.01
0.02
0.03
0.07
100 ms
0.1 0.2 0.5 2 5 10 501 20 100
D, DUTY CYCLE (%)
PULSE WIDTH
10 ms
APPLICATION NOTES
RESPONSE TIME
In most applications, the transient suppressor device is
placed in parallel with the equipment or component to be
protected. In this situation, there is a time delay associated
with the capacitance of the device and an overshoot
condition associated with the inductance of the device and
the inductance of the connection method. The capacitance
effect is of minor importance in the parallel protection
scheme because it only produces a time delay in the
transition from the operating voltage to the clamp voltage as
shown in Figure 8.
The inductive effects in the device are due to actual
turn‐on time (time required for the device to go from zero
current to full current) and lead inductance. This inductive
effect produces an overshoot in the voltage across the
equipment or component being protected as shown in
Figure 9. Minimizing this overshoot is very important in the
application, since the main purpose for adding a transient
suppressor is to clamp voltage spikes. These devices have
excellent response time, typically in the picosecond range
and negligible inductance. However, external inductive
effects could produce unacceptable overshoot. Proper
circuit layout, minimum lead lengths and placing the
suppressor device as close as possible to the equipment or
components to be protected will minimize this overshoot.
Some input impedance represented by Z
in
is essential to
prevent overstress of the protection device. This impedance
should be as high as possible, without restricting the circuit
operation.
DUTY CYCLE DERATING
The data of Figure 1 applies for non‐repetitive conditions
and at a lead temperature of 25°C. If the duty cycle increases,
the peak power must be reduced as indicated by the curves
of Figure 7. Average power must be derated as the lead or
ambient temperature rises above 25°C. The average power
derating curve normally given on data sheets may be
normalized and used for this purpose.
At first glance the derating curves of Figure 7 appear to be
in error as the 10 ms pulse has a higher derating factor than
the 10 ms pulse. However, when the derating factor for a
given pulse of Figure 7 is multiplied by the peak power value
of Figure 1 for the same pulse, the results follow the
expected trend.
1N6373 - 1N6381 Series (ICTE-5 - ICTE-36)
http://onsemi.com
5
TYPICAL PROTECTION CIRCUIT
V
in
V
L
V
V
in
V
in
(TRANSIENT)
V
L
t
d
V
V
L
V
in
(TRANSIENT)
Z
in
LOAD
OVERSHOOT DUE TO
INDUCTIVE EFFECTS
t
D
= TIME DELAY DUE TO CAPACITIVE EFFECT
t
t
Figure 8. Figure 9.
1N6373 - 1N6381 Series (ICTE-5 - ICTE-36)
http://onsemi.com
6
PACKAGE DIMENSIONS
MOSORB
CASE 41A-04
ISSUE D
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.335 0.374 8.50 9.50
INCHES
B 0.189 0.209 4.80 5.30
D 0.038 0.042 0.96 1.06
K 1.000 --- 25.40 ---
P --- 0.050 --- 1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. LEAD FINISH AND DIAMETER UNCONTROLLED
IN DIMENSION P.
4. 041A-01 THRU 041A-03 OBSOLETE, NEW
STANDARD 041A-04.
D
K
P
P
A
K
B
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1N6379RL4

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
ESD Suppressors / TVS Diodes 25.9V 1500W
Lifecycle:
New from this manufacturer.
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