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NCP5214EVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
NCP5214
http://onsemi.com
19
APPLICATION INFORMATION
Input Capacitor Selection for VDDQ Buck Regulator
The input capacitor is important for proper regulation
operation of the buck regulator. It minimizes the input
voltage ripple and current ripple from the power source by
providing a local loop for switching current. The input
capacitor should be placed close to the drain of the
high−side MOSFET and source of the low−side MOSFET
with short, wide traces for connection. The input capacitor
must have large enough rms ripple current rating to
withstand the large current pulses present at the input of the
bulk regulator due to the switching current. The required
input capacitor rms ripple current rating can be estimated
by the following with minimum V
IN
:
I
CIN(RMS)
w I
OUT
V
OUT
V
IN
*
ǒ
V
OUT
V
IN
Ǔ
2
Ǹ
(eq. 1)
Besides, the voltage rating of the input capacitor should
be at least 1.25 times of the maximum input voltage.
Capacitance of around 20 mF to 50 mF should be sufficient
for most DDR applications. Ceramic capacitors are the
most suitable choice of input capacitor for notebook
applications due to their low ESR, high ripple current, and
high voltage rating. POSCAP or OS−CON capacitors can
also be used since they have good ESR and ripple current
rating, but they are larger in size and more expensive.
Aluminum electrolytic capacitors are also a choice for their
high voltage rating and low cost, but several aluminum
capacitors in parallel should be used for the required ripple
current. If ceramic capacitors are used, X5R and X7R types
are preferred rather than the Y5V type since the X5R and
X7R types are ceramic capacitors and have smaller
tolerance and temperature coefficient.
Output Capacitor Selection for VDDQ Buck Regulator
The output filter capacitor plays an important role in
steady state output ripple voltage, load transient
requirement, and loop compensation stability. The ESR
and the capacitance of the output capacitor are the most
important parameters needed to be considered. In general,
the output capacitor must have small enough ESR for
output ripple voltage and load transient requirement.
Besides, the capacitance of the output capacitor should be
large enough to meet the overshoot and undershoot during
load transient. Since steady state output ripple voltage,
transient load undershoot and overshoot are the largest at
maximum V
IN
, the ESR and capacitance of output
capacitor should be estimated at the maximum V
IN
condition.
For steady output ripple voltage, both ESR and
capacitance of the output capacitor are the contributing
factors, however, the capacitor ESR is the dominant factor.
The output ripple voltage is calculated as follows:
V
ripple
+ I
L(ripple)
ESR )
I
L(ripple)
t
on
C
OUT
(eq. 2)
V
ripple
+
I
L(ripple)
ESR, for small t
on
and large C
OU
T
(eq.
3)
where I
L(ripple)
is the inductor ripple current, t
on
is on−time,
and C
OUT
is the output capacitance.
The inductor ripple current can be calculated by the
equation:
I
L(ripple)
+
(V
IN
−V
OUT
) V
OUT
L f
SW
V
IN
(eq. 4)
where L is the inductance and f
SW
is the switching
frequency. The output ripple voltage can be reduced by
either using the inductor with larger inductance or the
output capacitor with smaller ESR. Thus, the ESR needed
to meet the ripple voltage requirement can be obtained by:
ESR v
V
ripple
L f
SW
V
IN
(V
IN
−V
OUT
) V
OUT
(eq. 5)
The inductor ripple current is typically 30% of the
maximum load current and the ripple voltage is typically
2% of the output voltage. Thus, the above inequality can be
simplified to:
ESR v
0.02 V
OUT
0.3 I
LOAD(max)
(eq. 6)
For the load transient, the output capacitor contributes to
both the load−rise and the load−release responses. The
voltage undershoot during step−up load can be calculated
by the equation:
V
undershoot
+ DI
LOAD
ESR )
DI
LOAD
C
OUT
ǒ
1−
V
OUT
V
IN
f
SW
Ǔ
(eq.
7)
where DI
LOAD
is the change in output current. If the second
term is ignored, then it becomes the following inequality:
ESR v
V
undershoot
DI
LOAD
(eq. 8)
The maximum ESR requires to meet voltage undershoot
requirement at step−up load transient can be estimated
from the above inequality.
Then, the required output capacitor capacitance can be
obtained by the following:
C
OUT
w
DI
LOAD
V
undershoot
−DI
LOAD
ESR
ǒ
1−
V
OUT
V
IN
f
SW
Ǔ
(eq. 9)
The output voltage overshoot during load−release is
because the excessive stored energy in the inductor is
absorbed by the output capacitor. The overshoot voltage
can be calculated by the following equation:
V
overshoot
+
LI
2
STEP(peak)
) C
OUT
V
2
OUT
C
OUT
Ǹ
−V
OU
T
(eq. 1
0)
NCP5214
http://onsemi.com
20
Then the required output capacitor capacitance can be
estimated by:
C
OUT
w
L I
2
STEP(peak)
(V
overshoot
) V
OUT
)
2
−V
2
OUT
(eq. 11)
I
STEP(peak)
+ DI
LOAD
)
(V
IN
−V
OUT
) V
OUT
2L f
SW
V
IN
(eq. 12)
where I
STEP(peak)
is the load current step plus half of the
ripple current at the load release and DI
LOAD
is the change
in the output load current.
Besides, the ESR and the capacitance of the output filter
capacitor also contribute to double pole and ESR zero
frequencies of the output filter, and the poles and zeros
frequencies of the compensation network for close loop
stability. The compensation network will be discussed in
more detail in the Loop Compensation section.
Other parameters about output filter capacitor that
needed to be considered are the voltage rating and ripple
current rating. The voltage rating should be at least 1.25
times the output voltage and the rms ripple current rating
should be greater than the inductor ripple current. Thus, the
voltage rating and ripple current rating can be obtained by:
V
rating
w 1.25 V
OUT
(eq. 13)
I
COUT(RMS)
w I
L(ripple)
+
(V
IN
−V
OUT
) V
OUT
L f
SW
V
IN
(eq. 14)
SP−Cap, POSCAP and OS−CON capacitors are suitable
for the output capacitor since their ESR is low enough to
meet the ripple voltage and load transient requirements.
Usually, two or more capacitors of the same type,
capacitance and ESR can be used in parallel to achieve the
required ESR and capacitance without change the ESR
zero position for maintaining the same loop stability. Other
than the performance point of view, the physical size and
cost are also the concerned factors for output capacitor
selection.
Inductor Selection
The inductor should be chosen according to the inductor
ripple current, inductance, maximum current rating,
transient load release, and DCR.
In general, the inductor ripple current is 20% to 40% of
the maximum load current. A ripple current of 30% of the
maximum load current can be used as a typical value. The
required inductance can be estimated by:
L w
(V
IN
−V
OUT
) V
OUT
0.3 I
LOAD(max)
V
IN
f
SW
(eq. 15)
where I
LOAD(max)
is the maximum load current.
The DC current rating of the inductor should be about 1.2
times of the peak inductor current at maximum output load
current. Therefore, the maximum DC current rating of the
inductor can be obtained by:
I
L(rating)
+ 1.2 I
L(peak)
(eq. 16)
where I
L(peak)
is the peak inductor current at maximum load
current which is determined by:
I
L(peak)
+ I
LOAD(max)
)
I
L(ripple)
2
(eq. 17)
+ I
LOAD(max)
)
(V
IN
−V
OUT
) V
OUT
2 L f
SW
V
IN
Since the excessive energy stored in the inductor
contributed to the output voltage overshoot during load
release, the following inequality can be used to ensure that
the selected inductance value can meet the voltage
overshoot requirement at load release:
L v
C
OUT
((V
overshoot
) V
OUT
)
2
−V
2
OUT
)
I
2
STEP(peak)
(eq. 18)
In addition, the inductor also needs to have low enough
DCR to obtain good conversion efficiency. In general,
inductors with about 2.0 mW to 3.0 mW per mH of
inductance can be used. Besides, larger inductance value
can be selected to achieve higher efficiency as long as it
still meets the targeted voltage overshoot at load release
and inductor DC current rating.
MOSFET Selection
External N−channel MOSFETs are used as the switching
elements of the buck controller. Both high−side and
low−side MOSFETs must be logic−level MOSFETs which
can be fully turned on at 5.0 V gate−drive voltage.
On−resistance (R
DS(on)
), maximum drain−to−source
voltage (V
DSS
), maximum drain current rating, and gate
charges (Q
G
, Q
GD
, Q
GS
) are the key parameters to be
considered when choosing the MOSFETs.
For on−resistance, it should be the lower; the better is the
performance in terms of efficiency and power dissipation.
Check the MOSFET’s rated R
DS(on)
at V
GS
= 4.5 Vwhen
selecting the MOSFETs. The low−side MOSFET should
have lower R
DS(on)
than the high−side MOSFET since the
turn−on time of the low−side MOSFET is much longer than
the high−side MOSFET in high V
IN
and low V
OUT
buck
converter. Generally, high−side MOSFET with R
DS(on)
about 7.0 mW and low−side MOSFET with R
DS(on)
about
5.0 mW can achieve good efficiency.
The maximum drain current rating of the high−side
MOSFET and low−side MOSFET must be higher than the
peak inductor current at maximum load current. The
low−side MOSFET should have larger maximum drain
current rating than the high−side MOSFET since the
low−side MOSFET have longer turn−on time.
NCP5214
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21
The maximum drain−to−source voltage rating of the
MOSFETs used in buck converter should be at least 1.2 times
of the maximum input voltage. Generally, V
DSS
of 30 V
should be sufficient for both high−side MOSFET and
low−side MOSFET of the buck converter for notebook
application.
As a general rule of thumb, the gate charges are the
smaller; the better is the MOSFET while R
DS(on)
is still low
enough. MOSFETs are susceptible to false turn−on under
high dV/dt and high VDS conditions. Under high dV/dt and
high V
DS
condition, current will flow through the C
GD
of
the capacitor divider formed by C
GD
and C
GS
, cause the
C
GS
to charge up and the V
GS
to rise. If the V
GS
rises above
the threshold voltage, the MOSFET will turn on.
Therefore, it should be checked that the low−side MOSFET
have low Q
GD
to Q
GS
ratio. This indicates that the low−side
MOSFET have better immunity to short moment false
turn−on due to high dV/dt during the turn−on of the
high−side MOSFET. Such short moment false turn−on will
cause minor shoot−through current which will degrade
efficiency, especially at high input voltage condition.
Overcurrent Protection of VDDQ Buck Regulator
The OCP circuit is configured to set the current limit for
the current flowing through the high−side FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the high−side FET.
An internal 31 mA current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC and develops a voltage at the
non−inverting input of the current limit comparator.
Another voltage drop is established across the high−side
MOSFET R
DS(on)
at a magnitude of I
L
xR
DS(on)
and a
voltage is developed at SWDDQ when the high−side
MOSFET is turned on and the inductor current flows
through the R
DS(on)
of the MOSFET. The voltage at the
non−inverting input of the current limit comparator is then
compared to the voltage at SWDDQ pin when the
high−side gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than the voltage at the
non−inverting input of the current limit comparator for four
consecutive internal clock cycles, an overcurrent condition
occurs, during which, all outputs will be latched off to
protect against a short−to−ground condition on SWDDQ or
VDDQ. i.e., the voltage drop across the R
DS(on)
of
high−side FET developed by the drain current is larger than
the voltage drop across RL1, the OCP is triggered and the
device will be latched off.
The overcurrent protection will trip when a peak inductor
current hit the I
LIMIT
determined by the equation:
I
LIMIT
+
RL1 IOC
R
DS(on)
(eq. 19)
It should be noted that the OCDDQ pin must be pulled
high to VIN through a resistor RL1 and this pin cannot be
left floating for normal operation. The voltage drop across
RL1 must be less than 1.0 V to allow enough headroom for
the voltage detection at the OCDDQ pin under low VIN
condition. In addition, since the MOSFET R
DS(on)
varies
with temperature as current flows through the MOSFET
increases, the OCP trip point also varies with the MOSFET
R
DS(on)
temperature variation.
Since the IOC and R
DS(on)
have device variations and
MOSFET R
DS(on)
increase with temperature, to avoid false
triggering the overcurrent protection in normal operating
output load range, calculate the RL1 value from the
previous equation with the following conditions such that
minimum value of inductor current limit is set:
1. The minimum IOC value from the specification
table.
2. The maximum R
DS(on)
of the MOSFET used at
the highest junction temperature.
3. Determine I
LIMIT
for I
LIMIT
> I
LOAD(max)
+
I
L(ripple)/
2, where I
LOAD(max)
= I
VDDQ(max)
+
I
VTT(max)
if VTT is powered by VDDQ.
Besides, a decoupling capacitor C
DCPL
should be added
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the high−side MOSFET.
Loop Compensation
Once the output LC filter components have been
determined, the compensation network components can be
selected. Since NCP5214 is a voltage mode PWM
converter with output LC filter, Type III compensation
network is required to obtain the desired close loop
bandwidth and phase boost with unconditional stability.
The NCP5214 PWM modulator, output LC filter and
Type III compensation network are shown in Figure 39.
The output LC filter has a double pole and a single zero.
The double pole is due to the inductance of the inductor and
capacitance of the output capacitor, while the single zero
is due to the ESR and capacitance of the output capacitor.
The Type III compensation has two RC pole−zero pairs.
The two zeros are used to compensate the LC double pole
and provide 180° phase boost. The two poles are used to
compensate the ESR zero and provide controlled gain
roll−off. For an ideally compensated system, the Bode plot
should have the close−loop gain roll−off with a slope of
−20 dB/decade crossing the 0 dB with the required
bandwidth and the phase margin larger than 45° for all
frequencies below the 0 dB frequency. The closed loop
gain is obtained by adding the modulator and filter gain (in
dB) to the compensation gain (in dB).The bandwidth is the
frequency at which the gain is 0 dB and the phase margin
is the difference between the close loop phase and 180°.
The goal of compensation is to achieve a stable close loop
system with the highest possible bandwidth, the gain
having −20 dB/decade slope at 0 dB gain crossing, and
sufficient phase margin for stability. The bandwidth of
close loop gain should be less than 50% of the switching
frequency and the compensation gain should be bounded
by the error amplifier open loop gain.
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NCP5214EVB

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Power Management IC Development Tools ANA NCP5214 EVAL BRD
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