NCP5214EVB Datasheet NCP5214EVB, NCP5214MNR2G, NCP5214MNR2 | P25-P27

NCP5214

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Thus, inductor with 1.8 mH inductance, 14 A maximum

rated DC current and 3.5 mW DCR is chosen.

c. Calculate ESR and capacitance of output filter

capacitor:

First, the ESR required to achieve the desired output

ripple voltage is considered. Suppose the output ripple

voltage is 2% of the nominal output voltage.

ESR v

(0.02 1.8 V) 1.8 mH 400 kHz 20 V

(20 V−1.8 V) 1.8 V

(eq. 48)

+ 15.8 mW

Second, the ESR required to meet the transient load

undershoot requirement is considered, such that:

ESR v

100 mV

+ 14.3 mW

(eq. 49)

Therefore, the suitable ESR is 12 mW or smaller, and the

value of 7.5 mW is selected for more design margin and

better performance. Then, two same SP−Caps or POSCAPs

each with 15 mW ESR in parallel having a resultant ESR

of 7.5 mW should be good enough to meet the

requirements.

Then, check that whether the previously supposed

capacitance meets the undershoot and overshoot

requirements.

To ensure that undershoot requirement of less than 100 mV is achieved, the capacitance must be:

OUT

100 mV−7 A 7.5 mW

1−

1.8V−36mV

20 V

400 kHz

+ 335.9 mF

(eq. 50)

To make sure that overshoot requirement of less than 100 mV is fulfilled, capacitance must be:

OUT

1.8 mH

7A)

(20 V−1.836 V) 1.836 V

2 1.8 mH 400 kHz 20 V

(100 mV ) 1.836 V)

− (1.836 V)

+ 317.6 mF

(eq. 51)

Therefore, output capacitor with capacitance of 440 mF

should meet both undershoot and overshoot requirements.

Sometimes, it may take several times of iterations between

the process of selecting inductance of the inductor and ESR

and capacitance of the output capacitor.

Then, the voltage rating of the output capacitor is

estimated by:

rated

w 1.25 1.836 V + 2.3 V

(eq. 52)

Thus, output capacitor with 2.5 V or larger rated voltage

is used.

Finally, the rated rms ripple current of the output

capacitor is considered:

COUT(rms)

(20 V−1.836 V) 1.836 V

1.8 mH 400 kHz 20 V

+ 2.3 A

(eq. 53)

Thus, capacitor with rated rms ripple current of 3.0 A or

larger should be selected. Two capacitors each with 1.5 A

rated ripple current can be connected in parallel to provide

a total of 3.0 A rated rms ripple current.

Therefore, two same capacitors in parallel each with

capacitance of 220 mF, ESR of 15 mW, rated voltage of

2.5 V, and rated rms ripple current of 1.5 A are used.

d.Calculate the resistance value of OCP current limit

setting resistor:

First, the OCP current limit is estimated at maximum

load condition, such that:

LIMIT

u 8A) 2A)

(20 V−1.836 V) 1.836 V

2 1.8 mH 400 kHz 20 V

(eq. 54)

+ 11.16 A

Thus, I

LIMIT

is set to 11.5 A. Suppose from the high−side

MOSFET data sheet, the maximum R

DS(on)

is 10 mW.

Then, the value of RL1 is calculated by:

RL1 +

11.5 A 10 mW

26 mA

+ 4.4 kW

(eq. 55)

Therefore, the resistor with standard value of 4.7 kW is

selected for RL1.

e. Calculate the RC values of the compensation network:

First, 4.3 kW is chosen as the value of R

which is in the

range between 2.0 kW and 5.0 kW.

Since the worst case of stability is at the maximum V

the close loop compensation should be considered at

maximum V

. Then the ramp amplitude can be calculated

as below:

RAMP

+ 1.25 V ) 0.045 (20 V−5 V) + 1.925 V

(eq. 56)

Since the L = 1.8 mH, C

OUT

= 440 mF, and the target close loop bandwidth is 100 kHz, the value of R

can be

calculated as:

2p 100 kHz 1.925 V 4.3 kW 1.8 mH 440 mF

20 V

+ 7.3 kW

(eq. 57)

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Thus, standard value of 7.5 kW is selected for R

If the first zero break frequency is placed at half the LC

filter’s double pole, the value of C

can be calculated by:

2 1.8 mH 440 mF

7.5 kW

+ 7.5 nF

(eq. 58)

Thus, standard value of 8.2 nF is chosen for C2.

If the 1st pole break frequency is placed at the LC filter’s

ESR zero, the value of C

can be calculated by:

8.2 nF

+ 464.9 pF

(eq. 59)

7.5 kW 8.2 nF

7.5 mW 440 mF

* 1

Thus, standard value of 470 pF can be chosen for C

However, 180 pF is selected for more phase boost at the

0 dB gain crossing.

Then, if the second zero break frequency is placed at the LC

filter’s double pole and the second pole is placed at half the

switching frequency, the value of R

can be calculated by:

4.3 kW

p 400 kHz 1.8 mH 440 mF

−1

+ 125 W

(eq. 60)

Thus, standard value of 130 W is selected for R

Then, C

can be calculated by:

p 130 W 400 kHz

+ 6.12 nF

(eq. 61)

Therefore, standard value of 5.6 nF is selected for C

Then, the close loop phase margin can be estimated by the following:

Phase

(TypeIII)

+ −90 ) tan

−1

(2p 100 kHz 7.5 kW 8.2 nF)

(eq. 62)

−tan

−1

2p 100 kHz 7.5 kW

180 pF 8.2 nF

180 pF ) 8.2 nF

) tan

−1

(2p 100 kHz (4.3 kW ) 130 W) 5.6 nF)

−tan

−1

(2p 100 kHz 130 W 5.6 nF)

+ 20.57°

Phase

(Filter)

+ −tan

−1

(2p 100 kHz 7.5 mW 440 mF)

−tan

−1

2p 100 kHz 7.5 mW

2p (100 kHz)

1.8 mH 440 mF−1

+ −153.66°

Phase

(closeloop)

+ −153.66° ) 20.57° + −133.09°

Phase

(margin)

+ Phase

(closeloop)

−(−180°) + −133.09°−(−180°) + 46.91°

Therefore, the phase margin is large enough for stability.

f. Calculate the resistance value of feedback resistor

divider:

Since a 4.3 kW resistor is chosen as the high−side resistor

, the resistance value of low−side resistor R

can be

calculated by:

0.8 4.3 kW

1.8 V−0.8 V

+ 3.44 kW

(eq. 63)

Therefore, a 3.44 kW resistor is selected for the low−side

feedback resistor R

g.Calculate soft−start capacitor value for the desired

400 ms VDDQ soft−start time:

4.0 mA 400 ms

0.8 V

+ 2.0 nF

(eq. 64)

Therefore, 2.0 nF X5R ceramic capacitor is selected for

the soft−start capacitor.

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PCB Layout Guidelines

Cautious PCB layout design is very critical to ensure

high performance and stable operation of the DDR power

controller. The following items must be considered when

preparing PCB layout:

1. All high−current traces must be kept as short and

wide as possible to reduce power loss.

High−current traces are the trace from the input

voltage terminal to the drain of the high−side

MOSFET, the trace from the source of the

high−side MOSFET to the inductor, the trace

from inductor to the VDDQ output terminal, the

trace from the input ground terminal to the

VDDQ output ground terminal, the trace from

VDDQ output to VTTI pin, the trace from VTT

pin to VTT output terminal, and the trace from

VTT output ground terminal to the VTTGND pin.

Power handling and heaksinking of high−current

traces can be improved by also routing the same

high−current traces in the other layers and joined

together with multiple vias.

2. Power components which include the input

capacitor, high−side MOSFET, low−side

MOSFET and VDDQ output capacitor of the

buck converter section must be positioned close

together to minimize the current loop. The input

capacitor must be placed close to the drain of the

high−side MOSFET and the source of the

low−side MOSFET.

3. To ensure the proper function of the device,

separated ground connections should be used for

different parts of the application circuit according

to their functions. The input capacitor ground, the

low−side MOSFET source, the VDDQ output

capacitor ground, the VCCP decoupling capacitor

ground should be connected to the PGND. The

trace path connecting the source of the low−side

MOSFET and PGND pin should be minimized.

The VTT output capacitor ground should be

connected to the VTTGND first with a short

trace, it is then connected to the ground plane of

PGND. The VCCA decoupling capacitor ground,

the ground of the VDDQ feedback resistor, the

soft−start capacitor ground, the VTTREF output

capacitor ground should be connected to the

AGND. The AGND pin is then connected directly

through a sense trace to the remote ground sense

point of the PGND, which is usually the ground

of the local bypass capacitor for the load. Never

connect the AGND, PGND and VTTGND

together just under the thermal pad.

4. The thermal pad of the DFN−22 package should

be connected to the ground planes in the internal

layer and bottom layer from the copper pad at top

layer underneath the package through six to eight

vias with 0.6 mm hole−diameter to help heat

dissipation and ensure good thermal capability. It

is recommended to use PCB with 1 oz or 2 oz

copper foil. The thermal pad can be connected to

either PGND ground plane or AGND ground

plane but not both.

5. The input capacitor ground terminal, the VDDQ

output capacitor ground terminal and the source

of the low−side MOSFET must be connected to

the PGND ground plane through multiple vias.

6. Sensitive traces like trace from FBDDQ, trace

from COMP, trace from OCDDQ, trace from

FBVTT and trace from VTTREF should be

avoided from the high−voltage switching nodes

like SWDDQ, BOOST, TGDDQ and BGDDQ.

7. Separate sense trace should be used to connect

the VDDQ point of regulation, which is usually

the local bypass capacitor for load, to the

feedback resistor divider to ensure accurate

voltage sensing. The feedback resistor divider

should be place close to the FBDDQ pin.

8. Separate sense trace should be used to connect the

VTT point of regulation, which is usually the local

bypass capacitor for load, to the FBVTT pin.

9. Separate sense trace should be used to connect

the VDDQ point of regulation to the DDQREF

pin to ensure that the reference voltage to VTT is

accurately half of the VDDQ voltage.

10. The traces length between the gate driver outputs

and gates of the MOSFETs must be minimized to

avoid parasitic impedance.

11. To ensure normal function of the device, an RC

filter should be placed close to the VCCA pin and

a decoupling capacitor should be placed close to

the VCCP pin.

12. The copper trace area of the switching node which

includes the source of the high−side MOSFET,

drain of the low−side MOSFET and high voltage

side of the inductor should be minimized by using

short wide trace to reduce EMI.

13. A snubber circuit consists of a 3.3 W resistor and

1.0 nF capacitor may need to be connected across

the switching node and PGND to reduce the

high−frequency ringing occurring at the rising

edge of the switching waveform to obtain more

accurate inductor current limit sensing of the

VDDQ buck converter. However, adding this

snubber circuit will slightly reduce the conversion

efficiency.

14. VTTI should be connected to VDDQ output with

wide and short trace if VDDQ is used as the

sourcing supply for VTT. An input capacitor of at

least 10 mF should be added close to the VTTI

pin and bypassed to VTTGND if external voltage

supply is used as the VTT sourcing supply.

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NCP5214EVB

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Power Management IC Development Tools ANA NCP5214 EVAL BRD

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