10
FN8170.3
August 29, 2006
Figure 5. Three-Byte Instruction Sequence (Read Status Register)
Figure 6. Increment/Decrement Instruction Sequence
Figure 7. Increment/Decrement Timing Limits
WIP
Status
Bit
0101
A1 A0
I3
I2
I1
I0
RB RA
P0
SCL
SI
CS
00
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
00
0
0
0
00
00
101
1
0
0101
A1 A0
I3I2
I1
I0
RB RA P0
SCL
SI
CS
00
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
00
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
SCK
SI
R
W
INC/DEC CMD ISSUED
t
WRID
VOLTAGE OUT
X9260
11
FN8170.3
August 29, 2006
Table 5. Instruction Set
Note: 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3 I2 I1 I0 RB RA 0 P0
Read Wiper Counter
Register
1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter
Register pointed to by P0
Write Wiper Counter
Register
1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter
Register pointed to by P0
Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register
pointed to by P0 and RB - RA
Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register
pointed to by P0 and RB - RA
XFR Data Register to
Wiper Counter Register
1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register
pointed to by P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB - RA
Global XFR Data Registers
to Wiper Counter Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Control
Latch pointed to by P0
X9260
12
FN8170.3
August 29, 2006
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9260 on SO)
CS
Rising
Edge
010100A1A01001000P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
Edge
010100A1A01010000P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
010100A1A01011RBRA0 P0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01100RBRA0 P0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Rising
Edge
010100A1A00001RBRA00
X9260

X9260TS24Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs DL DCP 100KOHM 256 TAPS 2-WIRE
Lifecycle:
New from this manufacturer.
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