7
FN8170.3
August 29, 2006
Table 5. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
DEVICE DESCRIPTION
Instructions
I
DENTIFICATION BYTE ( ID AND A )
The first byte sent to the X9260 from the host,
following a CS
going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9260; this is fixed as
0101[B] (refer to Table 3).
The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9260
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9260 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V
CC
or V
SS
.
I
NSTRUCTION BYTE ( I[3:0] )
The next byte sent to the X9260 contains the instruction
and register pointer information. The three most
significant bits are used provide the instruction opcode
(I[3:0]). The RB and RA bits point to one of the four
Data Registers of each associated XDCP. The least
significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.
Table 3. Identification Byte Format
Table 4. Instruction Byte Format
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVV
(MSB) (LSB)
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
NV NV NV NV NV NV NV NV
MSB LSB
ID3 ID2 ID1 ID0 A3 A2 A1 A0
0101
(MSB) (LSB)
Device Type
Identifier
Slave Address
I3 I2 I1 I0 RB RA 0 P0
(MSB) (LSB)
Instruction
Data
Pot Selection
Opcode
Selection
(WCR Selection)
Register
X9260
8
FN8170.3
August 29, 2006
DEVICE DESCRIPTION
Instructions
Four of the ten instructions are three bytes in length.
These instructions are:
Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
Read Data Register – read the contents of the
selected Data Register;
Write Data Register – write a new value to the
selected Data Register.
Read Status - This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
WRL
. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique format (See Figure 5).
Four instructions require a two-byte sequence to
complete. These instructions transfer data between
the host and the X9260; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
XFR Data Register to Wiper Counter Register
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
XFR Wiper Counter Register to Data Register
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.
Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (See
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9260 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
HIGH
) while SI is HIGH,
the selected wiper will move one resistor segment
towards the R
H
terminal. Similarly, for each SCL clock
pulse while SI is LOW, the selected wiper will move
one resistor segment towards the R
L
terminal. A
detailed illustration of the sequence and timing for this
operation are shown. See Instruction format for more
details.
X9260
9
FN8170.3
August 29, 2006
Figure 2. Two-Byte Instruction Sequence
Figure 3. Three-Byte Instruction Sequence (Write)
Figure 4. Three-Byte Instruction Sequence (Read)
ID3 ID2 ID1 ID0 0
A1 A0
I3
I2
I1
RB RA P0
SCK
SI
CS
0101
Device ID
Internal
Instruction
Opcode
Address
Register
0
I0
Address
Pot/WCR
Address
0
0
0
0101
A1 A0
I3 I2
I1
I0
RB RA P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
00
WCR[7:0]
or
Data Register Bit [7:0]
0
0101
A1 A0
I3
I2
I1
I0
RB RA P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
00
WCR[7:0]
S0
X
X
X
XX
XX
X
Don’t Care
or
Data Register Bit [7:0]
0
X9260

X9260TS24Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs DL DCP 100KOHM 256 TAPS 2-WIRE
Lifecycle:
New from this manufacturer.
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