NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
PSMN075-100MSE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved
Product data sheet 26 March 2013 6 / 13
Symbol Parameter Conditions Min Typ Max Unit
Dynamic characteristics
I
D
= 5 A; V
DS
= 50 V; V
GS
= 10 V;
T
j
= 25 °C; Fig. 14; Fig. 15
- 16.4 - nCQ
G(tot)
total gate charge
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V;
T
j
= 25 °C
- 12.9 - nC
Q
GS
gate-source charge - 3.1 - nC
Q
GS(th)
pre-threshold gate-
source charge
- 2.1 - nC
Q
GS(th-pl)
post-threshold gate-
source charge
I
D
= 5 A; V
DS
= 50 V; V
GS
= 10 V;
T
j
= 25 °C; Fig. 14; Fig. 15
- 1 - nC
Q
GD
gate-drain charge I
D
= 5 A; V
DS
= 50 V; V
GS
= 10 V;
T
j
25 °C; Fig. 14; Fig. 15
- 5.3 - nC
V
GS(pl)
gate-source plateau
voltage
I
D
= 5 A; V
DS
= 50 V; T
j
= 25 °C;
Fig. 14; Fig. 15
- 4.3 - V
C
iss
input capacitance - 773 - pF
C
oss
output capacitance - 66 - pF
C
rss
reverse transfer
capacitance
V
DS
= 50 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; Fig. 16
- 48 - pF
t
d(on)
turn-on delay time - 5.5 - ns
t
r
rise time - 5.8 - ns
t
d(off)
turn-off delay time - 12.4 - ns
t
f
fall time
V
DS
= 50 V; R
L
= 10 Ω; V
GS
= 10 V;
R
G(ext)
= 5 Ω; T
j
= 25 °C
- 6.2 - ns
Source-drain diode
V
SD
source-drain voltage I
S
= 15 A; V
GS
= 0 V; T
j
= 25 °C; Fig. 17 - 0.89 1.2 V
t
rr
reverse recovery time - 35.8 - ns
Q
r
recovered charge
I
S
= 5 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 50 V; T
j
= 25 °C
- 50.7 - nC
