MAX1471
coding, which has an equal number of zeros and ones,
is used.
Figure 5 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Peak Detectors
The maximum peak detectors (PDMAXA for ASK,
PDMAXF for FSK) and minimum peak detectors (PDMI-
NA for ASK, PDMINF for FSK), in conjunction with resis-
tors and capacitors shown in Figure 5, create DC
output voltages proportional to the high and low peak
values of the filtered ASK or FSK demodulated signals.
The resistors provide a path for the capacitors to dis-
charge, allowing the peak detectors to dynamically fol-
low peak changes of the data-filter output voltages.
The maximum and minimum peak detectors can be
used together to form a data-slicer threshold voltage at
a midvalue between the maximum and minimum volt-
age levels of the data stream (see the
Data Slicers
sec-
tion and Figure 5). The RC time constant of the peak-
detector combining network should be set to at least 5
times the data period.
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX1471 has a fea-
ture called peak-detector track enable (TRK_EN),
where the peak-detector outputs can be reset (see
Figure 6). If TRK_EN is set (logic 1), both the maximum
and minimum peak detectors follow the input signal.
When TRK_EN is cleared (logic 0), the peak detectors
revert to their normal operating mode. The TRK_EN
function is automatically enabled for a short time and
then disabled whenever the IC recovers from the sleep
portion of DRX mode, or when an AGC gain switch
occurs. Since the peak detectors exhibit a fast
attack/slow decay response, this feature allows for an
extremely fast startup or AGC recovery. See Figure 7
for an illustration of a fast-recovery sequence. In addi-
tion to the automatic control of this function, the
TRK_EN bits can be controlled through the serial inter-
face (see the
Serial Control Interface
section).
If the peak detectors are not used, make sure that the
FSKPD_EN and ASKPD_EN bits in Register 0x0 are
maintained at the default setting of logic 0 and short
each of the four PD pins directly to ground or through a
capacitor whose value is approximately 1000pF. If a
peak detector pin is left open, the FDATA and ADATA
signals can potentially couple back into the DSA+ or
the DSA- lines (depending on circuit design and lay-
out), causing an oscillation at the output of the data
slicer comparator. The PDMINA peak detector is partic-
ularly vulnerable to this coupling because its pin (31) is
next to the ADATA pin (30).
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
14 ______________________________________________________________________________________
Figure 3. Sallen-Key Lowpass Data Filter
