MAX1471
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace con-
necting a 100nH inductor adds an extra 10nH of induc-
tance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power lane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all V
DD
or HVIN connections.
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
22 ______________________________________________________________________________________
Table 7. Configuration Register (Address: 0x1)
BIT ID BIT NAME
BIT LOCATION
(0 = LSB)
POWER-UP
STATE
FUNCTION
X Don’t care 7 0 Don’t care.
GAINSET Gain set 6 1
0 = LNA low-gain state.
1 = LNA high-gain state.
For manual gain control, enable the AGC (AGC_EN =
1), set LNA gain state to desired setting, then disable
the AGC (AGC_EN = 0).
FSKCALLSB
FSK accurate
calibration
50
FSKCALLSB = 1 enables a longer, more accurate
FSK calibration.
FSKCALLSB = 0 provides for a quick, less accurate
FSK calibration.
DOUT_FSK FSKOUT enable 4 0
This bit enables the FDATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)
DOUT_ASK ASKOUT enable 3 0
This bit enables the ADATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)
TOFF_PS1 Off-timer prescale 2 0
TOFF_PS0 Off-timer prescale 1 0
Sets LSB size for the off timer. (See the Off Timer
section.)
DRX_MODE Receive mode 0 0
1 = Discontinuous receive mode. (See the
Discontinuous Receive Mode section.)
0 = Continuous receive mode. (See the Continuous
Receive Mode section.)
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
______________________________________________________________________________________ 23
Table 8. Control Register (Address: 0x2)
BIT ID BIT NAME
BIT LOCATION
(0 = LSB)
POWER-UP
STATE
FUNCTION
X None 7 Don’t care Don’t care.
AGCLOCK AGC lock 6 0 Locks the LNA gain in its present state.
X None 5, 4 Don’t care.
FSKTRK_EN
FSK peak
detector track
enable
30
Enables the tracking mode of the FSK peak detectors
when FSKTRK_EN = 1. (See the Peak Detectors
section.)
ASKTRK_EN
ASK peak
detector track
enable
20
Enables the tracking mode of the ASK peak detectors
when ASKTRK_EN = 1.
(See the Peak Detectors section.)
POL_CAL_EN
Polling timer
calibration enable
10
POL_CAL_EN = 1 starts the polling timer calibration.
Calibration of the polling timer is needed when using
the MAX1471 in discontinous receive mode.
POL_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
FSK_CAL_EN
FSK calibration
enable
00
FSK_CAL_EN starts the FSK receiver calibration.
FSK_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
Table 9. Status Register (Read Only) (Address: 0x9)
BIT ID BIT NAME
BIT LOCATION
(0 = LSB)
FUNCTION
LOCKDET Lock detect 7
0 = Internal PLL is not locked so the MAX1471 will not receive data.
1 = Internal PLL is locked.
AGCST AGC state 6
0 = LNA in low-gain state.
1 = LNA in high-gain state.
CLKALIVE
Clock/crystal
alive
5
0 = No valid clock signal seen at the crystal inputs.
1 = Valid clock at crystal inputs.
X None 4, 3, 2 Don’t care.
POL_CAL_DONE
Polling timer
calibration done
1
0 = Polling timer calibraton in progress or not completed.
1 = Polling timer calibration is complete.
FSK_CAL_DONE
FSK calibration
done
0
0 = FSK calibration in progress or not completed.
1 = FSK calibration is compete.
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
24 ______________________________________________________________________________________
Figure 12. DRX Mode Sequence of the MAX1471
ADATA OR
FDATA
t
OFF
t
OFF
DIO
t
CPU
t
RF
CS
t
CPU
t
LOW
t
RF
Table 12. RF Settle Timer (t
RF
)
Configuration
TIME BASE
(1 LSB)
MIN t
RF
REG 0x7 = 0x00
REG 0x8 = 0x01
MAX t
RF
REG 0x7 = 0xFF
REG 0x8 = 0xFF
120µs 120µs 7.86s
Table 10. Off-Timer (t
OFF
) Configuration
PRESCALE1 PRESCALE0
t
OFF
TIME BASE
(1 LSB)
MIN t
OFF
REG 0x4 = 0x00
REG 0x5 = 0x01
MAX t
OFF
REG 0x4 = 0xFF
REG 0x5 = 0xFF
0 0 120µs 120µs 7.86s
0 1 480µs 480µs 31.46s
1 0 1920µs 1.92ms 2 min 6s
1 1 7680µs 7.68ms 8 min 23s
Table 11. CPU Recovery Timer (t
CPU
)
Configuration
TIME BASE
(1 LSB)
MIN t
CPU
REG 0x6 = 0x01
MAX t
CPU
REG 0x6 = 0xFF
120µs 120µs 30.72ms

MAX1471ATJ+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
RF Receiver 315MHz/434MHz Superheterodyne Rcvr
Lifecycle:
New from this manufacturer.
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