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PCK351DB,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
1. General description
The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The PCK351
enables a single clock input to be distributed to ten outputs with minimum output skew and
pulse skew. The use of distributed V
CC
and GND pins in the PCK351 ensures reduced
switching noise.
The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and over
the industrial temperature range −40 °Cto+85°C.
2. Features
■ 1 : 10 LVTTL clock distribution
■ Low output-to-output skew
■ Low output pulse skew
■ Overvoltage tolerant inputs and outputs
■ LVTTL-compatible inputs and outputs
■ Distributed V
CC
and ground pins reduce switching noise
■ Balanced high-drive outputs (−32 mA I
OH
, 32 mA I
OL
)
■ Reduced power dissipation due to the state-of-the-art QUBiC-LP process
■ Supply range of +3.0 V to +3.6 V
■ Package options include plastic small-outline (D) and shrink small-outline (DB)
packages
■ Industrial temperature range −40 °Cto+85°C
PCK351
1 : 10 clock distribution device with 3-state outputs
Rev. 02 — 16 December 2005 Product data sheet
PCK351_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 16 December 2005 2 of 18
Philips Semiconductors
PCK351
1 : 10 clock distribution device with 3-state outputs
3. Quick reference data
[1] C
PD
is used to determine the dynamic power dissipation (P in µW).
P=C
PD
× V
CC
2
× f
i
+ ∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in volts.
4. Ordering information
Table 1: Quick reference data
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
≤
3.0 ns.
Symbol Parameter Conditions Min Typ Max Unit
t
PLH
LOW-to-HIGH
propagation delay
A input to Yn outputs;
C
L
= 50 pF; V
CC
= 3.3 V
3.1 3.6 4.1 ns
t
PHL
HIGH-to-LOW
propagation delay
A input to Yn outputs;
C
L
= 50 pF; V
CC
= 3.3 V
3.1 3.6 4.1 ns
C
i
input capacitance V
CC
= 3.3 V; V
I
=V
CC
or GND;
f=10MHz
-4-pF
C
o
output capacitance V
CC
= 3.3 V; V
O
=V
CC
or GND;
f=10MHz
-6-pF
C
PD
power dissipation
capacitance
[1]
C
L
= 50 pF; f = 1 MHz - 48 - pF
Table 2: Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number Package
Name Description Version
PCK351D SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
PCK351DB SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
PCK351_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 16 December 2005 3 of 18
Philips Semiconductors
PCK351
1 : 10 clock distribution device with 3-state outputs
5. Functional diagram
Fig 1. Logic diagram of PCK351
002aaa282
23
21
19
18
16
14
11
9
4
2
6
5
OE
A
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

PCK351DB,118

Mfr. #:
Buy PCK351DB,118
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 1:10 125MHZ 24SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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