LT1766/LT1766-5
25
1766fc
RiseTime
RC V
V
SS OUT
BE
=
()( )( )
4
Using the values shown in Figure 10,
Rise Time ms=
()( )
()
=
47 10 15 10 5
07
5
39
••
.
–
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 generates both positive and nega-
tive 5V outputs with a single piece of magnetics. The two
inductors shown are actually just two windings on a stan-
dard Coiltronics inductor. The topology for the 5V output
is a standard buck converter. The – 5V topology would be
a simple fl yback winding coupled to the buck converter
if C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a fl yback converter, during
switch on-time, all the converter’s energy is stored in L1A
only, since no current fl ows in L1B. At switch off, energy
V
OUT1
5V
(SEE DN100
FOR MAX I
OUT
)
V
OUT2
–5V
†
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX50-3A
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 10MQ060N
V
IN
7.5V
TO 60V
GND
1766 F14
C2
0.33μF
C
F
220pF
D1
C1
100μF
10V
TANT
C5
100μF
10V
TANT
C3
2.2μF
100V
CER
C4
100μF
10V
TANT
D2
1N4148W
D3
L1A*
50μH
L1B*
R1
15.4k
R2
4.99k
++
+
R
C
2.2k
C
C
0.022μF
BOOST
V
IN
LT1766
SHDN
SYNC
SW
FB
V
C
GND
Figure 14. Dual Output SEPIC Converter
OUTPUT
5V
1A
INPUT
40V
1766 F13
C2
0.33μF
C1
100μF
C
SS
15nF
C
F
220pF
D1
C3
2.2μF
50V
CER
D2
1N4148W
L1
47μH
R1
15.4k
R3
2k
C
C
0.022μF
R2
4.99k
R4
47k
Q1
BOOST BIAS
V
IN
LT1766
SHDN
SYNC
SW
FB
V
C
GND
+
R
C
2.2k
Figure 13. Buck Converter with Adjustable Soft-Start
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on-time,
causing current to fl ow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur-
rents, see Design Note 100.
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT1766 accepts only positive feedback signals.
The ground pin must be tied to the regulated negative
output. A resistor divider to the FB pin then provides the
proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
I
I
VV
VVfL
VV
VV VV
MAX
P
IN OUT
OUT IN
OUT IN
OUT IN OUT F
=
+
⎡
⎣
⎢
⎤
⎦
⎥
++
–
()( )
()()()
()(–.)
(–.)()
2
03
03
APPLICATIONS INFORMATION