8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout notes:
1. Separate Xout and Xin Traces by 3 x the trace width
2. Do not share crystal load capacitor ground via with
other components.
3. Route power from bead through bulk capacitor pad
then through 0.1uF capacitor pad then to clock chip
Vdd pad.
4. Do not share ground vias. One ground pin one ground
via.
Revision history: 0.1 3/26/2015 first publication
LVDS TERMINATION
3.3V LVPECL TERMINATION
2.5V and 3.3V
HCSL TERMINATION
LVCMOS TERMINATION
Manufacture Part Number Z@100MHz PkgSz DC res. Current(Ma)
Fair-Rite 2504021217Y0 120 0402 0.5 200
muRata BLM15AG221SN1 220 0402 0.35 300
muRata BLM15BB121SN1 120 0402 0.35 300
TDK MMZ1005S241A 240 0402 0.18 200
TECSTAR TB4532153121 120 0402 0.3 300
NOTE:FERRITE BEAD FB1, FB2=
LP HCSL TERMINATION FOR OUT3/3B,
OUT5/5B to OUT11/11B
the following pins have weak pull-down resistors: 12,13,14,33,24 and 47
PLACE NEAR
I2C CONTROLLER
IF USED
NOTE:VCC
can be set
to 1.8V,2.5V
or 3.3V
FG_X1
OUT_0_SEL-I2C
V1P8VCB
OUTR0
V1P8VCB
OUTR1
OUTRB1
V1P8VCB
OUTR2
OUTRB2
OUTR3
OUTRB3
V1P8VCB
OUTR4
OUTRB4
OUTR2
OUT_2
FG_X2
SDA
SCL
V1P8VCA
V1P8VC
V1P8VCA
OUTR5
OUTRB5
OUTR6
OUTRB6
OUTR7
OUTRB7
OUTR8
OUTRB8
OUTR9
OUTRB9
OUTR10
OUTRB10
OUTR11
OUTRB11
OE_buffer
OEB7_10
OEB3,11
SD/OE
V1P8VCA
V1P8VCB
V1P8VC
OUTR3
OUTRB3
OUT_0_SEL-I2C
SDA
SCL
V1P8VC
V1P8VCA
VCC
VCC1P8
V1P8VC
V3P3
Size
Document Number Re v
Date: Sheet
of
0.1
Integrated Device Technology
A
11Thursday, March 26, 2015
5P49V5908_SCH
San Jose, CA
Size
Document Number Re v
Date: Sheet
of
0.1
Integrated Device Technology
A
11Thursday, March 26, 2015
5P49V5908_SCH
San Jose, CA
Size
Document Number Re v
Date: Sheet
of
0.1
Integrated Device Technology
A
11Thursday, March 26, 2015
5P49V5908_SCH
San Jose, CA
R3 100
1 2
U2
RECEIVER
1
2
R12 50
1 2
U7
RECEIVER
1
2
R5
49.9
1%
1 2
C10
.1uF
12
U4
RECEIVER
1
2
C9
10uF
12
R14 33
1 2
C8
.1uF
12
FB2
SIGNAL_BEAD
1 2
R11 50
1 2
R7
10K
1 2
C11
.1uF
12
R10 50
1 2
C1
10uF
12
C5
.1uF
12
R8
10K
1 2
R2
2.2
1 2
FB1
SIGNAL_BEAD
1 2
R6
33
1 2
C3
.1uF
12
R4
49.9
1%
1 2
C4
.1uF
12
U5
5P49V5908A
XOUT
2
XIN/REF
3
NC
32
VDDO
5
OUT7
10
SEL1/SDA
13
SEL0/SCL
14
SD/OE
12
VDDA
4
VDD
15
VDDO0
46
OUT0_SEL_I2CB
47
VDDO1
39
OUT1
38
OUT1B
37
VDDO2
36
OUT2
35
OUT2B
34
VDD_CORE
30
OUT3
29
OUT3B
28
VDDO4
21
OUT4
22
OUT4B
23
EPAD
49
EPAD
50
EPAD
51
EPAD
52
EPAD
53
EPAD
54
EPAD
55
EPAD
56
OUT5B
20
OUT5
19
VDDO
27
OUT6B
18
OUT6
17
OUT7B
11
NC
25
NC
26
VDD
31
VDD
44
VDDO
43
NC
40
OEB7_10
33
OE_buffer
45
OUT8
8
OUT8B
9
OUT9
6
OUT9B
7
OUT10
48
OUT10B
1
OUT11
41
OUT11B
42
OEB3,11
24
VDDO
16
EPAD
57
EPAD
58
R15
33
1 2
R18
10K
1 2
C7
NP
12
C2
1uF
12
R13 33
1 2
R17 33
1 2
R16 33
1 2
GNDGND
Y1
25.000 MHz
CL = 8pF
4
1
2
3
U3
RECEIVER
1
2
C6
NP
12
