MAX2981
Detailed Description
The MAX2981 powerline communication AFE and line-
driver IC is a state-of-the-art CMOS device that delivers
high performance at low cost. This highly integrated
design combines an ADC, DAC, AGC, filters, and line
driver on a single chip as shown in the
Functional
Diagram
. The MAX2981 substantially reduces previous-
ly required system components and complies with the
HomePlug 1.0 standard.
Combined with Maxim’s integrated PHY/MAC digital
baseband, the device delivers the most flexible and
cost-effective solution. The advanced design of the
MAX2981 allows operation without external control,
enabling simplified connection to a variety of HomePlug
1.0 digital PHY ICs.
Receive Channel
The receiver analog front-end consists of a variable-
gain amplifier (VGA), a lowpass filter (LPF), a highpass
filter (HPF), and an AGC circuit. An ADC block samples
the AGC output. The ADC communicates to the digital
PHY chip through a mux block.
The VGA reduces the receive channel input-referred
noise by providing some signal gain to the AFE input.
The filter blocks remove unwanted noise, and provide the
anti-aliasing required by the ADC for accurate sampling.
The AGC scales the signal for conversion from analog
to digital. The scaling maintains the optimum signal
level at the ADC input and keeps the AGC amplifiers
out of saturation.
The 10-bit ADC samples the analog signal at 50Msps
and converts it to a 10-bit digital stream. The block fully
integrates reference voltages and biasing for the input
differential signal.
Transmit Channel
The transmit channel consists of a 10-bit DAC, a LPF,
and an adjustable-gain transmitter buffer and line dri-
ver. The DAC receives the data stream from the digital
PHY IC through the mux block.
The 50MHz, 10-bit DAC provides the complementary
function to the receive channel. The DAC converts the 10-
bit digital stream to an analog voltage at a 50MHz rate.
The LPF removes spurs and harmonics adjacent to the
desired passband to help reduce the out-of-band trans-
mitted frequencies and energy from the DAC output.
The transmit buffer and line-driver blocks allow the out-
put level of the LPF to obtain a level necessary to con-
nect directly to the powerline medium, without the use
of external amplifiers and buffers. The output level is
adjustable from 1.4V
P-P
to 4.0V
P-P
differential. The line
driver can drive resistive loads as low as 10Ω single-
ended.
Line Driver Bypass
Use register R6B[2:1] to bypass the line driver. With the
line driver bypassed, the output can drive a 50Ω single-
ended external load.
Digital Interface
The digital interface is composed of control signals and
a 10-bit bidirectional data bus for the DAC and ADC.
The control signals include a reset line, a transmit
request, an I/O direction request, and a receiver shut-
down control.
Integrated Powerline Communication Analog
Front-End Transceiver and Line Driver
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Functional Diagram
