Control Signals
Transmit Enable (ENTX)
The ENTX line enables the transmitter of the MAX2981
AFE circuit. With ENTX and ENREAD driven high, data
sent to the DAC through DAD[9:0] is conditioned and
delivered onto the power line.
Read Enable (ENREAD)
The ENREAD line sets the direction of the data bus
DAD[9:0]. With ENREAD high, data is sent from the dig-
ital PHY to the DAC in the MAX2981 AFE. A low on
ENREAD sends data from the ADC to the digital PHY.
Receiver Power-Down (SHRCV)
The SHRCV line provides receiver shutdown control. A
logic-high on SHRCV powers down the receiver section
of the MAX2981 whenever the device is transmitting. The
MAX2981 also features a transmit power-saving mode,
which reduces supply current from 350mA to 150mA. To
enter the transmit power-saving mode, drive SHRCV
high 0.1µs prior to the end of transmission. Connect
SHRCV to ENTX and ENREAD for normal operation.
Digital-to-Analog and Analog-to-Digital Converter
Input/Output (DAD[9:0])
DAD[9:0] is the 10-bit bidirectional bus connecting the
digital PHY to the MAX2981 DAC and ADC. The bus
direction is controlled by ENREAD, as described in the
Read Enable (ENREAD)
section.
AGC Control Signal (CS)
The CS signal controls the AGC circuit of the receive
path in the MAX2981. A logic-low on CS sets the gain
circuit on the input signal to continuously adapt for
maximum sensitivity. A valid preamble detected by the
digital PHY raises CS to high. While CS is high, the
AGC continues to adapt for an additional 8µs; then the
AGC locks the currently adapted level on the incoming
signal. The digital PHY holds CS high while receiving a
transmission, and then lowers CS for continuous adap-
tation for maximum sensitivity of other incoming signals.
AGC Freeze Mode (FREEZE)
Use the FREEZE signal to instantly lock the AGC gain.
Clock (CLK)
The CLK signal provides all timing for the MAX2981.
Apply a 50MHz clock to this input. See the timing dia-
gram (Figure 1) for more information.
Reset Input (RESET)
The RESET signal provides reset control for the
MAX2981. To perform a reset, set CLK in free-running
mode and drive RESET low for a minimum of 100ns.
Always perform a reset at power-up.
Standby Control (STBY)
The MAX2981 features a low-power, shutdown mode
that is activated by STBY. Drive STBY high to place
the MAX2981 in standby mode. In standby, the
MAX2981 consumes only 20mA with a clock and 5mA
without a clock.
MAX2981 Control Registers
MAX2981 Serial Interface
The 3-wire serial interface controls the MAX2981 opera-
tion mode. The SCLK is the serial clock line for register
programming. The SDIO is the I/O serial data input and
output for register writing or reading. The SWR signal
controls the write/read mode of the serial interface.
If SWR is high, the serial interface is in write mode and
a new value can be written into the MAX2981 registers.
Following SWR low-to-high transitions, data is shifted
synchronously (LSB first) to registers on the falling
edge of the serial clock (SCLK) as illustrated in Figure
2. Note that one extra clock (WR_CLK) is required to
write the content of holding the buffer to the appropri-
ate register bank.
If SWR is low, the serial interface is in read mode and
the value of the current register can be read. The read
operation to a specific register must be followed imme-
diately after writing to the same register. Following SWR
high-to-low transitions, data is shifted synchronously
(LSB first) to registers on the falling edge of the serial
clock (SCLK) as illustrated in Figure 3.
The MAX2981 has a set of six read/write registers; bits
A2, A1, A0 are the register address bits.
MAX2981
Integrated Powerline Communication Analog
Front-End Transceiver and Line Driver
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