MPC9230
Rev. 5, 08/2005
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
800 MHz Low Voltage PECL
Clock Synthesizer
The MPC9230 is a 3.3 V compatible, PLL based clock synthesizer targeted for
high performance clock generation in mid-range to high-performance telecom,
networking and computing applications. With output frequencies from 50 MHz to
800 MHz
(1)
and the support of differential PECL output signals the device meets
the needs of the most demanding clock applications.
Features
50 MHz to 800 MHz
(1)
synthesized clock output signal
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference clock input
3.3 V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP and 28-lead PLCC packaging
32-lead and 28-lead Pb-free package available
SiGe Technology
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MC12430
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800
to 1600 MHz.
(1)
Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator
frequency f
XTAL
, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 8M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz
(1)
). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to V
CC
– 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD
input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs and prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the program-
ming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in
the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
1. The VCO frequency range of 800–1600 MHz is available at an ambient temperature range of 0 to 70°C. At –40 to +85°C, the VCO frequency
(output frequency) is limited to max. 1500 MHz (750 MHz).
MPC9230
800 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
EI SUFFIX
28-LEAD PLCC PACKAGE
Pb-FREE PACKAGE
CASE 776-02
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Advanced Clock Drivers Devices
2 Freescale Semiconductor
MPC9230
Figure 1. MPC9230 Logic Diagram
Figure 2. MPC9230 28-Lead PLCC Pinout
(Top View)
Figure 3. MPC9230 32-Lead Package Pinout
(Top View)
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
M[0:8]
XTAL
PLL
Ref
FB
VCO
800 – 1800 MHz
11
00
01
10
9-BIT M-Divider
M-Latch N-Latch
10 – 20 MHz
T-Latch
9
2
Test
3
LE
01 01
Bits 5-13
Bits 3-4
Bits 0-2
14-Bit Shift Register
N[1:0]
OE
P/S
÷1
÷2
÷4
÷8
FOUT
Test
OE
FREF_EXT
XTAL_SEL
P_LOAD
F
OUT
V
CC
V
CC
V
CC
÷
16
÷
2
÷0
TO ÷511
÷
2
1
4
3
2
28
27
26
25 24 23 22 21 20 19
18
17
16
15
14
13
12
111097865
V
CC
XTAL_OUT
P_LOAD
OE
M[0]
M[1]
M[2]
M[3]
FOUT
GND
V
CC
TEST
GND
S_CLOCK
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
S_DATA
S_LOAD
V
CC_PLL
FREF_EXT
XTAL_SEL
XTAL_IN
MPC9230
F
OUT
GND
TEST
V
CC
V
CC
GND
FOUT
NC
M[3]
M[2]
M[1]
M[0]
P_LOAD
NC
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
S_CLOCK
S_LOAD
V
CC_PLL
V
CC_PLL
FREF_EXT
XTAL_SEL
XTAL_IN
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
V
CC
OE
XTAL_OUT
S_DATA
MPC9230
F
OUT
Advanced Clock Drivers Devices
Freescale Semiconductor 3
MPC9230
Table 1. Pin Configurations
Pin I/O Default Type Function
XTAL_IN, XTAL_OUT Analog Crystal oscillator interface
FREF_EXT Input 0 LVCMOS Alternative PLL reference input
F
OUT
, F
OUT
Output LVPECL Differential clock output
TEST Output LVCMOS Test and device diagnosis output
XTAL_SEL Input 1 LVCMOS PLL reference select input
S_LOAD Input 0 LVCMOS Serial configuration control input
This input controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD Input 1 LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD
.
P_LOAD
is state sensitive.
S_DATA Input 0 LVCMOS Serial configuration data input
S_CLOCK Input 0 LVCMOS Serial configuration clock input
M[0:8] Input 1 LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD
N[1:0] Input 1 LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
OE Input 1 LVCMOS Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the F
OUT
output
GND Supply Ground Negative power supply (GND)
V
CC
Supply V
CC
Positive power supply for I/O and core. All V
CC
pins must be connected to the
positive power supply for correct operation
V
CC_PLL
Supply V
CC
PLL positive power supply (analog power supply)
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
for T
A
= 0°C to +70°C
Output Frequency Range
for T
A
= –40°C to +85°C
1 0
0 0 2 200 – 400 MHz 200 – 375 MHz
0 1 4 100 – 200 MHz 100 – 187.5 MHz
1 0 8 50 – 100 MHz 50 – 93.75 MHz
1 1 1 400 – 800 MHz 400 – 750 MHz
Table 3. Function Table
Input 0 1
XTAL_SEL FREF_EXT XTAL interface
OE Outputs disabled. F
OUT
is stopped in the logic low state
(F
OUT
= L, F
OUT
= H)
Outputs enabled

MPC9230FN

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner FSL 800MHz LVPECL Freq. Synthesizer
Lifecycle:
New from this manufacturer.
Delivery:
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