Advanced Clock Drivers Devices
4 Freescale Semiconductor
MPC9230
Table 4. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
– 2 V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 2000 V
LU Latch-Up Immunity 200 mA
C
IN
Input Capacitance 4.0 pF Inputs
θ
JA
LQFP 32 Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θ
JC
LQFP 32 Thermal Resistance Junction to Case 23.0 26.3 °C/W MIL-SPEC 883E
Method 1012.1
Table 5. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit Condition
V
CC
Supply Voltage –0.3 4.6 V
V
IN
DC Input Voltage –0.3 V
CC
+ 0.3 V
V
OUT
DC Output Voltage –0.3 V
CC
+ 0.3 V
I
IN
DC Input Current ±20 mA
I
OUT
DC Output Current ±50 mA
T
S
Storage Temperature –65 125 °C
Table 6. DC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
Symbol Characteristics Min Typ Max Unit Condition
LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
I
IN
Input Current
(1)
1. Inputs have pull-down resistors affecting the input current.
±200 µA V
IN
= V
CC
or GND
Differential Clock Output F
OUT
(2)
2. Outputs terminated 50 to V
TT
= V
CC
– 2 V.
V
OH
Output High Voltage V
CC
–1.02 V
CC
–0.74 V LVPECL
V
OL
Output Low Voltage V
CC
–1.95 V
CC
–1.60 V LVPECL
Test and Diagnosis Output TEST
V
OH
Output High Voltage V
CC
–1.02 V
CC
–0.74 V LVPECL
V
OL
Output Low Voltage V
CC
–1.95 V
CC
–1.60 V LVPECL
Supply Current
I
CC_PLL
Maximum PLL Supply Current 20 mA V
CC_PLL
Pins
I
CC
Maximum Supply Current 110 mA All V
CC
Pins
Advanced Clock Drivers Devices
Freescale Semiconductor 5
MPC9230
Table 7. AC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= –40°C to +85°C)
Symbol Characteristics Min Typ Max Unit Condition
LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
I
IN
Input Current
(1)
1. Inputs have pull-down resistors affecting the input current.
±200 µA V
IN
= V
CC
or GND
Differential Clock Output F
OUT
(2)
2. Outputs terminated 50 to V
TT
= V
CC
– 2 V.
V
OH
Output High Voltage V
CC
–1.1 V
CC
–0.74 V LVPECL
V
OL
Output Low Voltage V
CC
–1.95 V
CC
–1.65 V LVPECL
Test and Diagnosis Output TEST
V
OH
Output High Voltage V
CC
–1.1 V
CC
–0.74 V LVPECL
V
OL
Output Low Voltage V
CC
–1.95 V
CC
–1.65 V LVPECL
Supply Current
I
CC_PLL
Maximum PLL Supply Current 20 mA V
CC_PLL
Pins
I
CC
Maximum Supply Current 110 mA All V
CC
Pins
Advanced Clock Drivers Devices
6 Freescale Semiconductor
MPC9230
Table 8. AC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
XTAL
Crystal Interface Frequency Range 10 20 MHz
f
REF
FREF_EXT Reference Frequency Range 10 (f
VCO,MAX
÷M)4
(2)
2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable
PLL operation.
MHz
f
VCO
VCO Frequency Range
(3)
3. The input frequency f
XTAL
and the PLL feedback divider M must match the VCO frequency range: f
VCO
= f
XTAL
M ÷ 4.
800 1600 MHz
f
MAX
Output Frequency N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
400
200
100
50
800
400
200
100
MHz
MHz
MHz
MHz
f
S_CLOCK
Serial Interface Programming Clock Frequency
(4)
4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
0 10 MHz
t
P,MIN
Minimum Pulse Width (S_LOAD, P_LOAD) 50 ns
DC Output Duty Cycle 45 50 55 %
t
r
, t
f
Output Rise/Fall Time 0.05 0.3 ns 20% to 80%
t
S
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
t
H
Hold Time S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
t
JIT(CC)
Cycle-to-Cycle Jitter N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
80
90
130
160
ps
ps
ps
ps
t
JIT(PER)
Period Jitter N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
60
70
120
140
ps
ps
ps
ps
t
LOCK
Maximum PLL Lock Time 10 ms

MPC9230FN

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner FSL 800MHz LVPECL Freq. Synthesizer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet