STK672-732AN-E
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6
Sample Application Circuit
Precautions
[GND wiring]
To reduce noise on the 5 V / 24 V system, be sure to place the GND of C01 in the circuit given above as close as possible
to Pin 2 and Pin 6 of the IPM.
In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared ground
terminal used by the Pin 18 (S.G) GND, P.G1 and P.G2.
[Input pins]
If V
DD
is being applied, use care that each input pin does not apply a negative voltage less than 0.3 V to S. GND,
Pin 18. Measures must also be taken so that a voltage equal to or greater than V
DD
is not input.
Do not wire by connecting the circuit pattern on the P.C.B side to Pins 4, 8, or 11 on the N.C. shown in the internal
block diagram.
Apply 2.5 V high level input to pins 10, 12, 13, 14, 15, and 17.
Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17
are used as inputs, a 1 to 20 k pull-up resistor (to V
DD
) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down to
less than 0.8 V at Low level (less than 0.8 V at Low level when I
OL
= 5 mA).
[Current setting Vref]
Considering the specifications for the Vref input bias current IIB, we recommend a value 1 k or less for R02.
If the motor current is temporarily reduced, the circuit given below (STK672-732AN : I
OH
> 0.2 A) is recommended.
5 V
R01
R02
R3
5 V
R02
R3
Vref
Vref
R01
STK672
-73xAN-E
+
9
13
17
12
10
15
14
16
19
18
6
2
7
5
1
3
V
DD
(5V)
ΦA
ΦAB
ΦB
ΦBB
ENABLE
RESETB
FAULT
A
AB
B
BB
Vref
R01
R03
R02
S.G
P.G1
P.G2
P.GND
V
CC
24V
C01
at least 100F
2 phase stepper motor driver
+
C02
10F
