Rev. 2.1 May 2012
www.aosmd.com
Page 5 of 8
AOZ8808
High Speed PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8808DI devices should be located as close as
possible to the noise source. The AOZ8808DI device
should be placed on all data and power lines that enter or
exit the PCB at the I/O connector. In most systems, surge
pulses occur on data and power lines that enter the PCB
through the I/O connector. Placing the AOZ8808DI
devices as close as possible to the noise source ensures
that a surge voltage will be clamped before the pulse can
be coupled into adjacent PCB traces. In addition, the
PCB should use the shortest possible traces. A short
trace length equates to low impedance, which ensures
that the surge energy will be dissipated by the
AOZ8808DI device. Long signal traces will act as
antennas to receive energy from fields that are produced
by the ESD pulse. By keeping line lengths as short as
possible, the efficiency of the line to act as an antenna for
ESD related fields is reduced. Minimize interconnecting
line lengths by placing devices with the most interconnect
as close together as possible. The protection circuits
should shunt the surge voltage to either the reference or
chassis ground. Shunting the surge voltage directly to the
IC’s signal ground can cause ground bounce. The
clamping performance of TVS diodes on a single ground
PCB can be improved by minimizing the impedance with
relatively short and wide ground traces. The PCB layout
and IC package parasitic inductances can cause
significant overshoot to the TVS’s clamping voltage. The
inductance of the PCB can be reduced by using short
trace lengths and multiple layers with separate ground
and power planes. One effective method to minimize
loop problems is to incorporate a ground plane in the
PCB design.
The AOZ8808DI ultra-low capacitance TVS is designed
to protect four high speed data transmission lines from
transient over-voltages by clamping them to a fixed
reference. The low inductance and construction
minimizes voltage overshoot during high current surges.
When the voltage on the protected line exceeds the
reference voltage the internal steering diodes are forward
biased, conducting the transient current away from the
sensitive circuitry. The AOZ8808DI is designed for ease
of PCB layout by allowing the traces to run underneath
the device. The pinout of the AOZ8808DI is designed to
simply drop onto the IO lines of a High Definition
Multimedia Interface (HDMI) or USB 3.0 design without
having to divert the signal lines that may add more
parasitic inductance. Pins 1, 2, 4 and 5 are connected to
the internal TVS devices and pins 6, 7, 9 and 10 are no
connects. The no connects was done so the package can
be securely soldered onto the PCB surface.
Figure 3. Flow Through Layout for HDMI Figure 4. Flow Through Layout for USB 3.0
.
Clock
Data0
Ground
Data1
Data2
Clock
Data0
Ground
Data1
Data2
SSRX+
SSRX–
Ground
SSTX+
SSTX–
SSRX+
SSRX–
Ground
SSTX+
SSTX–
