HMC5883
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MODES OF OPERATION
This device has several operating modes whose primary purpose is power management. This section describes these
modes.
Continuous-Measurement Mode
During continuous-measurement mode, the device continuously makes measurements and places measured data in data
output registers. Settings in the configuration register affect the data output rate (bits DO[n]), the measurement
configuration (bits MS[n]), and the gain (bits GN[n]) when in continuous-measurement mode. To conserve current
between measurements, the device is placed in a state similar to idle mode, but the mode is not changed to idle mode.
That is, MD[n] bits are unchanged. Data can be re-read from the data output registers if necessary; however, if the
master does not ensure that the data register is accessed before the completion of the next measurement, the new
measurement may be lost. All registers maintain values while in continuous-measurement mode. The I
2
C bus is enabled
for use by other devices on the network in while continuous-measurement mode.
Single-Measurement Mode
This is the default single supply power-up mode. In dual supply configuration this is the default mode when AVDD goes
high. During single-measurement mode, the device makes a single measurement and places the measured data in data
output registers. Settings in the configuration register affect the measurement configuration (bits MS[n]), and the gain
(bits GN[n]) when in single-measurement mode. After the measurement is complete and output data registers are
updated, the device is placed sleep mode, and the mode register is changed to sleep mode by setting MD[n] bits. All
registers maintain values while in single-measurement mode. The I
2
C bus is enabled for use by other devices on the
network while in single-measurement mode.
Idle Mode
During this mode the device is accessible through the I
2
C bus, but major sources of power consumption are disabled,
such as, but not limited to, the ADC, the amplifier, the SVDD pin, and the sensor bias current. All registers maintain
values while in idle mode. The I
2
C bus is enabled for use by other devices on the network while in idle mode.
Sleep Mode
This is the default dual supply power-up mode when only DVDD goes high and AVDD remains low. During sleep mode
the device functionality is limited to listening to the I
2
C bus. The internal clock is not running and register values are not
maintained while in sleep mode. The only functionality that exists during this mode is the device is able to recognize and
execute any instructions specific to this device but does not change from sleep mode due to other traffic on the I
2
C bus.
The I
2
C bus is enabled for use by other devices on the network while in sleep mode. This mode has two practical
differences from idle mode. First this state will create less noise on system since the clock is disabled, and secondly this
state is a lower current consuming state since the clock is disabled.
Off Mode
During off mode device is off. No device functionality exists. Both AVDD and DVDD are low. The I
2
C bus is enabled for
use by other devices on the network in off mode. In this mode the I
2
C pins shall be in a high impedance state.
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REGISTERS
This device is controlled and configured via a number of on-chip registers, which are described in this section. In the
following descriptions, set implies a logic 1, and reset or clear implies a logic 0, unless stated otherwise.
Register List
The table below lists the registers and their access. All address locations are 8 bits.
Address Location
Name
Access
00
Configuration Register A
Read/Write
01
Configuration Register B
Read/Write
02
Mode Register
Read/Write
03
Data Output X MSB Register
Read
04
Data Output X LSB Register
Read
05
Data Output Z MSB Register
Read
06
Data Output Z LSB Register
Read
07
Data Output Y MSB Register
Read
08
Data Output Y LSB Register
Read
09
Status Register
Read
10
Identification Register A
Read
11
Identification Register B
Read
12
Identification Register C
Read
Table 5: Register List
Register Access
This section describes the process of reading from and writing to this device. The devices uses an address pointer to
indicate which register location is to be read from or written to. These pointer locations are sent from the master to this
slave device and succeed the 7-bit address plus 1 bit read/write identifier.
To minimize the communication between the master and this device, the address pointer updated automatically without
master intervention. This automatic address pointer update has two additional features. First when address 12 or higher
is accessed the pointer updates to address 00 and secondly when address 09 is reached, the pointer rolls back to
address 03. Logically, the address pointer operation functions as shown below.
If (address pointer = 09) then address pointer = 03
Else if (address pointer >= 12) then address pointer = 0
Else (address pointer) = (address pointer) + 1
The address pointer value itself cannot be read via the I
2
C bus.
Any attempt to read an invalid address location returns 0’s, and any write to an invalid address location or an undefined bit
within a valid address location is ignored by this device.
To move the address pointer to a random register location, first issue a “write” to that register location with no data byte
following the commend. For example, to move the address pointer to register 10, send 0x3C 0x0A.
HMC5883
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Configuration Register A
The configuration register is used to configure the device for setting the data output rate and measurement configuration.
CRA0 through CRA7 indicate bit locations, with CRA denoting the bits that are in the configuration register. CRA7 denotes
the first bit of the data stream. The number in parenthesis indicates the default value of that bit.
CRA7
CRA6
CRA5
CRA4
CRA3
CRA2
CRA1
CRA0
(0)
(0)
(0)
DO2 (1)
DO1 (0)
DO0 (0)
MS1 (0)
MS0 (0)
Table 6: Configuration Register A
Location
Name
Description
CRA7 to CRA5
0
These bits must be cleared for correct operation.
CRA4 to CRA2
DO2 to DO0
Data Output Rate Bits. These bits set the rate at which
data is written to all three data output registers.
CRA1 to CRA0
MS1 to MS0
Measurement Configuration Bits. These bits define the
measurement flow of the device, specifically whether or
not to incorporate an applied bias to the sensor into the
measurement.
Table 7: Configuration Register A Bit Designations
The Table below shows all selectable output rates. All three channels shall be measured within a given output rate. Other
output rates with maximum rate of 116 Hz can be achieved by monitoring DRDY interrupt pin in single measurement
mode. DRDY pin is normally high and is low for 5 µsec when data is placed in the output registers.
DO2
DO1
DO0
Typical Data Output Rate (Hz)
0
0
0
0.75
0
0
1
1.5
0
1
0
3
0
1
1
7.5
1
0
0
15 (default)
1
0
1
30
1
1
0
75
1
1
1
Not used
Table 8: Data Output Rates
MS1
MS0
Mode
0
0
Normal measurement configuration (default). In normal measurement
configuration the device follows normal measurement flow. The positive and
negative pins of the resistive load are left floating and high impedance.
0
1
Positive bias configuration for X and Y axes, negative bias configuration for
Z axis. In this configuration, a positive current is forced across the resistive
load for X and Y axes, a negative current for Z axis.
1
0
Negative bias configuration for X and Y axes, positive bias configuration for
Z axis. In this configuration, a negative current is forced across the resistive
load for X and Y axes, a positive current for Z axis.
1
1
This configuration is not used.
Table 9: Measurement Modes

103040000

Mfr. #:
Manufacturer:
Seeed Studio
Description:
Magnetic Sensor Development Tools Xadow - Compass
Lifecycle:
New from this manufacturer.
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