ADP5073CP-EVALZ/ADP5074CP-EVALZ User Guide UG-1157
Rev. 0 | Page 3 of 8
EVALUATION BOARD HARDWARE
EVALUATION BOARD CONFIGURATIONS
The ADP5073CP-EVALZ and the ADP5074CP-EVALZ
evaluation boards are configured to provide a −5 V output
from a +3 V to +13.2 V input.
Table 2 and Table 3 in the Ordering Information section of this
user guide list the components for both the ADP5073CP-EVALZ
and ADP5074CP-EVALZ boards, respectively.
The board allows the end user to customize the design. Refer to
the ADP5073 and ADP5074 data sheets or to the corresponding
ADIsimPower tool to obtain alternative component values.
Figure 2 shows the board features available to the user.
POWE
OUTPUT
POWE
INPUT
GND GND–+
ENABLE PROTECTION
PROVIDES SUITABLE ENABLE
VOLTAGE, V_EN, ACROSS VIN
RANGE (IN COMBINATION WITH R1,
R2 AND CR2); FOR EFFICIENCY
MEASUREMENT, DISCONNECT
V_EN AND THEN PROVIDE AN
EXTERNAL ENABLE SIGNAL
SLEW RATE
SLOW =AGND
NORMAL = VREG
FAST = NO CONNECT
POWER GOOD
THIS PIN IS AN OPEN-DRAIN, POWER-
GOOD INDICATOR AND IS PULLED UP
O THE ON-BOARD ENABLE VOLTAGE,
V_EN, BY THE PG RESISTOR RPG.
SWITCHING FREQUENCY
EXTERNAL CLOCK CAN BE
CONNECTED TO CENTER PIN
(5.5V MAXIMUM)
SOFT START
R
SS
CONTROLS SOFT START RATE;
REMOVE JUMPER TO DISCONNECT
RESISTOR
ENABLE
EXTERNAL ENABLE SIGNAL
CAN BE CONNECTED TO
CENTER PIN (5.5V MAXIMUM)
16037-002
Figure 2. Outline of ADP5073/ADP5074 Evaluation Board Features
Table 1. ADP5073CP-EVALZ/ADP5074CP-EVALZ Function Descriptions
Jumper/Connector
Mnemonic
Description
VIN Power Supply to the ADP5073/ADP5074. In the default configuration, this ranges from 3 V to 13.2 V.
VOUT Output from the ADP5073/ADP5074. VOUT is −5 V in default configuration.
V_EN
Provides a clamped enable voltage to allow operation using input voltages higher than 5.5 V, without damaging
the EN pin. For efficiency measurements, remove this jumper and provide an enable signal from an external supply.
EN
Precision Enable. The EN pin is compared to an internal precision reference to enable the inverting regulator
output. Connect this jumper to the on position to turn on the regulator. Connect this jumper to the off position or
remove this jumper to turn the regulator off (an internal pull down is present in the ADP5073/ADP5074). An
external enable can be connected to the center pin with a voltage from 1.2 V to 5.5 V.
SYNC/FREQ
Synchronization Input and Frequency Setting. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high.
To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency,
connect the SYNC/FREQ pin to an external clock (5.5 V maximum).
SLEW
Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW pin driver. For the fastest slew rate (best
efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the slowest slew
rate (best electromagnetic interference (EMI) performance), connect the SLEW pin to GND.
SS
Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start
time, connect this jumper. This jumper connects the RSS resistor between the SS pin and GND.
PG
Power-Good Output. This pin is an open-drain, power-good indicator and is pulled up to the on-board enable
voltage, V_EN, by the RPG resistor.
