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Data subject to change. Copyright © 2016 Avago Technologies. All rights reserved. Obsoletes AV01-0556EN
AV02-0674EN - September 30, 2016
120 pF
18
27
36
45
1
2
HCPL-2201/11
HCPL-02XX
HCNW22XX
DATA INPUT
TTL OR LSTTL
V
CC2
(+5 V)
UP TO 16 LSTTL LOADS
OR 4 TTL LOADS
*
* 0.1 μF BYPASS
1.1 kΩ
80 Ω
V
CC1
(+5 V)
DATA OUTPUT
120 pF*
18
27
36
45
1
2
HCPL-2201/11
HCPL-02XX
HCNW22XX
DATA INPUT
TTL OR LSTTL
V
CC2
(4.5 TO 20 V)
**0.1 μF BYPASS
1.1 kΩ
80 Ω*
V
CC1
(+5 V)
DATA OUTPUT
TOTEM
POLE
OUTPUT
GATE
* 120 pF PEAKING CAPACITOR
MAY BE OMITTED AND 80 Ω
RESISTOR MAY BE SHORTED
WHERE 500 ns PROPAGATION
DELAY IS SUFFICIENT.
V
CC
GND
CMOS
V
CC2
5 V
10 V
15 V
20 V
R
L
1.1 kΩ
2.37 kΩ
3.83 kΩ
5.11 kΩ
R
L
18
27
36
45
HCPL-2201/11
HCPL-02XX
HCNW22XX
DATA
INPUT
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
1.1 kΩ
V
CC1
(+5 V)
V
CC
GND
D1
TTL or
LSTTL
120 pF*
18
27
36
45
HCPL-2201/11
HCPL-02XX
HCNW22XX
DATA INPUT
TTL OR LSTTL
1.1 kΩ
80 Ω*
V
CC
(+5 V)
OPEN
COLLECTOR
GATE
* 120 pF PEAKING CAPACITOR
MAY BE OMITTED AND 80 Ω
RESISTOR MAY BE SHORTED
WHERE 500 ns PROPAGATION
DELAY IS SUFFICIENT.
V
CC
GND
4.7 kΩ
Figure 16. Series LED drive with open collector gate
(4.7 k resistor shunts I
OH
from the LED).
Figure 14. LSTTL to CMOS interface circuit.
Figure 15. Alternative LED drive circuit.
Figure 13b. Recommended LSTTL to LSTTL circuit for applications requiring a maximum allowable propagation delay of 300 ns.
