Rev. 1.1 6/18 Copyright © 2018 by Silicon Laboratories Si597
QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
O
SCILLATOR (VCXO) 10 TO 810 MHZ
Features
Applications
Description
The Si597 quad frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low-jitter clock for all output frequencies. The
Si597 is available with one of four pin-selectable ouput frequencies from 10
to 810 MHz. Unlike traditional VCXOs, where a different crystal is required
for each output frequency, the Si597 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides supply noise rejection, simplifying
the task of generating low-jitter clocks in noisy environments. The Si597 IC-
based quad frequency VCXO is factory-configurable for a wide variety of
user specifications including frequencies, supply voltage, output format,
tuning slope, and absolute pull range (APR). Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Available with any-frequency
output from 10 to 810 MHz
4 selectable output frequencies
3rd generation DSPLL
®
with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
OTN
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Any Frequency
10–810 MHz
DSPLL
Clock Synthesis
CLK+
CLK-
V
DD
Power Supply Filtering
Power Supply Filtering
OE
GND
Control
FS0
FS1
Fixed
Frequency
Oscillator
V
c
ADC
Ordering Information:
See page 8.
Pin Assignments:
See page 7.
(Top View)
Si5602
1
2
3
6
5
4
V
C
GND
OE
V
DD
CLK+
CLK–
7
8
FS[1]
FS[0]
Si597
Si597
2 Rev. 1.1
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. Si597 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Si597
Rev. 1.1 3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage
1
V
DD
3.3 V option 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75 V
1.8 V option 1.71 1.8 1.89 V
Supply Current I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
120
110
100
90
135
120
110
100
mA
mA
mA
mA
Tristate mode 60 75 mA
Output Enable (OE)
2
and
Frequency Select (FS[1:0])
V
IH
0.75 x V
DD
——V
V
IL
——0.5V
Operating Temperature Range T
A
–40 85 °C
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.
2. OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 8. FS[1:0] includes internal 17 kpull-up to
VDD.
Table 2. V
C
Control Voltage Input
Parameter Symbol Test Condition Min Typ Max Unit
Control Voltage Tuning Slope
1,2,3
K
V
10 to 90% of V
DD
45
95
125
185
380
ppm/V
Control Voltage Linearity
4
L
VC
BSL –5 ±1 +5 %
Incremental –10 ±5 +10 %
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
V
C
Input Impedance Z
VC
500 k
V
C
Input Capacitance C
VC
—50—pF
Nominal Control Voltage V
CNOM
@ f
O
—V
DD
/2 V
Control Voltage Tuning Range V
C
0—V
DD
V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.
2. For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3. K
V
variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.

597FE000700DG

Mfr. #:
Manufacturer:
Silicon Labs
Description:
XTAL OSC VCXO 2.5V 8SMD
Lifecycle:
New from this manufacturer.
Delivery:
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