QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1151
16-BIT HIGH SPEED SERIAL OUTPUT ADC
5
POWER
If a DC890 is used to acquire data from the
DC1151, the DC890 must be provided with an ex-
ternal 6V±0.5V 1A supply on turrets G7(+) and G1(-
) or the adjacent 2.1mm power jack to support the
power requirements of the Xilinx Spartan 3 FPGA.
The DC890B will not enable collection mode with-
out externally applied power present. Apply +3.3V
across the pins marked “EX_3.3V” and “GND” on
the DC1151. The DC1151 demonstration circuit re-
quires up to 500mA depending on the sampling rate
and the A/D converter supplied.
ENCODE CLOCK
NOTE: This is not a logic compatible input. Apply
an encode clock to the SMA connector on the
DC1151 demonstration circuit board marked “J5
ENCODE”. The transformer is terminated on the
secondary side with 100 ohms, and further termi-
nated at the ADC (at C12).
For the best noise performance, the ENCODE
CLOCK must be driven with a very low jitter source.
When using a sinusoidal generator, the amplitude
should be large, up to 2V
P-P
or 19dBm. Using band
pass filters on the clock and the analog input will
improve the noise performance by reducing the
wideband noise power of the signals. Data sheet
FFT plots are taken with 10 pole LC filters made by
TTE (Los Angeles, CA) to suppress signal generator
harmonics, non-harmonically related spurs and
broad band noise. Low phase noise Agilent 8644B
generators are used with TTE band pass filters for
both the Clock input and the Analog input.
ANALOG INPUT NETWORK
Apply the analog input signal of interest to the SMA
connectors on the DC1151 demonstration circuit
board marked “J2 SIG IN”. These inputs are ca-
pacitive coupled to Balun transformers ETC1-1-13,
or directly coupled through Flux coupled transform-
ers ETC1-1T. (See Schematic)
For optimal distortion and noise performance the
RC network on the analog inputs should be opti-
mized for different analog input frequencies. Refer
to the provided schematics. These two input net-
works cover a broad bandwidth and are not opti-
mized for operation at a specific input frequency.
For input frequencies less than 5MHz, or greater
than 150MHz, other input networks may be more
appropriate.
In almost all cases, filters will be required on both
analog input and encode clock to provide data sheet
SNR. In some cases, 3-10dB pads may be required
to obtain low distortion.
If your generator cannot deliver full scale signals
without distortion, you may benefit from a medium
power amplifier based on a Gallium Arsenide Gain
block prior to the final filter. This is particularly true
at higher frequencies where IC based operational
amplifiers may be unable to deliver the combination
of low noise figure and High IP3 point required. A
high order filter can be used prior to this final am-
plifier, and a relatively low Q filter used between the
amplifier and the demo circuit.
DIGITAL OUTPUTS
The LTC2274 family has a high speed serial output.
The output data is serialized according to the JEDEC
specification for serial converters (JESD204).
The LTC2274 family uses CML drivers to transmit
high-speed data. The output driver bias current is
typically 16mA, generating a signal swing potential of
400mVpp (800mVdiff) across the combined internal
and external termination resistance of 20ohms on
each output.
The standard DC1151 demo board is configured to be
used with the DC890. Capacitors C26 and C27 are in
the “A” position. This drives the output of the
LTC2274 into an 8B/10B decoder that also de-
serializes the data for use with the parallel connector
of the DC890. If an FPGA is used to receive the CML
output signals directly, capacitors C26 and C27 should
be moved to position “B” and the jumper on JP2
should be moved to SHDN. This drives the CML out-
