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MC14012BDR2G

P1-P3P4-P6P7-P7
MC14012B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol V
DD
Vdc
Min Typ
(Note 6)
Max Unit
Output Rise Time
t
TLH
= (1.35 ns/pF) C
L
+ 33 ns
t
TLH
= (0.60 ns/pF) C
L
+ 20 ns
t
TLH
= (0.40 ns/PF) C
L
+ 20 ns
t
TLH
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Output Fall Time
t
THL
= (1.35 ns/pF) C
L
+ 33 ns
t
THL
= (0.60 ns/pF) C
L
+ 20 ns
t
THL
= (0.40 ns/pF) C
L
+ 20 ns
t
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 115 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 47 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 37 ns
t
PLH
, t
PHL
5.0
10
15
−
−
−
160
65
50
300
130
100
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
14
C
L
V
SS
7
PULSE
GENERATOR
INPUT
OUTPUT
90%
50%
10%
10%
50%
90%
20 ns 20 ns
t
PHL
t
PLH
t
TLH
t
THL
V
OL
V
OH
0 V
V
DD
INPUT
OUTPUT
INVERTING
*All unused inputs of AND, NAND gates must be connected to V
DD
.
All unused inputs of OR, NOR gates must be connected to V
SS
.
90%
50%
10%
V
OL
V
OH
OUTPUT
NON−INVERTING
t
THL
t
TLH
t
PLH
t
PHL
*
Figure 3. Switching Time Test Circuit and Waveforms
14
*
7
1, 13
V
SS
V
DD
*Inverter omitted
2, 9
3, 10
V
DD
V
SS
SAME AS
ABOVE
4, 11
5, 12
Figure 4. Circuit Schematic − One of Two Gates Shown
MC14012B
http://onsemi.com
5
TYPICAL B−SERIES GATE CHARACTERISTICS
N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE)
−40°C
+85°C
+125°C
Figure 5. V
GS
= 5.0 Vdc Figure 6. V
GS
= − 5.0 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0 3.0 5.04.02.00
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
−1.0
0
0
T
A
= −55°C
Figure 7. V
GS
= 10 Vdc Figure 8. V
GS
= − 10 Vdc
16
14
12
10
8.0
6.0
4.0
2.0
0
5.03.01.0 108.06.04.02.0
0
0
0
Figure 9. V
GS
= 15 Vdc Figure 10. V
GS
= − 15 Vdc
0
0
0
0
−40°C
+25°C
+85°C
+125°C
−1.0 −3.0 −5.0−4.0−2.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
T
A
= −55°C
+25°C
T
A
= −55°C
−40°C
+25°C
+85°C
+125°C
V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc) V
DS
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
T
A
= −55°C
−40°C
+ 25°C
+85°C
+125°C
18
20
9.07.0 −5.0−3.0−1.0 −1
0
−8.0−6.0−4.0−2.0 −9.0−7.0
−40
−35
−30
−25
−20
−15
−10
−5.0
−45
−50
106.02.0 2016128.04.0 1814
T
A
= −55°C
−40°C
+25°C
+85°C
−10−6.0−2.0
−2
0
−16−12−8.0−4.0 −18−14
- 80
- 70
- 60
- 50
- 40
- 30
- 20
- 10
- 90
- 100
40
35
30
25
20
15
10
5.0
45
50
T
A
= −55°C
−40°C
+25°C
+85°C
−2.0
−3.0
−4.0
−5.0
−6.0
−7.0
−8.0
−9.0
−10
I ,
D
DRAIN CURRENT (mA)
I ,
D
DRAIN CURRENT (mA)
I ,
D
DRAIN CURRENT (mA)
I ,
D
DRAIN CURRENT (mA)
I ,
D
DRAIN CURRENT (mA)
I ,
D
DRAIN CURRENT (mA)
+125°C
+125°C
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
MC14012B
http://onsemi.com
6
VOLTAGE TRANSFER CHARACTERISTICS
Figure 11. V
DD
= 5.0 Vdc Figure 12. V
DD
= 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0 3.0 5.04.02.0
0
0
0
V
in
, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0 6.0 108.04.0
V
in
, INPUT VOLTAGE (Vdc)
V ,
out
OUTPUT VOLTAGE (Vdc)
V ,
out
OUTPUT VOLTAGE (Vdc)
Figure 13. V
DD
= 15 Vdc
0
0
SINGLE INPUT NAND, AN
D
MULTIPLE INPUT NOR, O
R
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND
, A
2.0
6.0
10
8.0
4.0
2.0 6.0 108.04.0
V
in
, INPUT VOLTAGE (Vdc)
12
14
16
V ,
out
OUTPUT VOLTAGE (Vdc)
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V
IL
and V
IH
for the output(s) to
be at a fixed voltage V
O
are given in the Electrical
Characteristics table. V
IL
and V
IH
are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 14. DC Noise Immunity
V
out
V
O
V
O
V
IL
0
V
IH
V
in
V
DD
V
DD
V
out
V
O
V
O
V
IL
0
V
IH
V
in
V
DD
V
DD
(a) Inverting Function (b) Non−Inverting Function
V
SS
= 0 VOLTS DC
P1-P3P4-P6P7-P7

MC14012BDR2G

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Buy MC14012BDR2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates 3-18V Dual 4-Input NAND
Lifecycle:
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