AS7C31026C-12TINTR

September 2006
Advance Information
Copyright © Alliance Memory. All rights reserved.
AS7C31026C
3.3 V 64K X 16 CMOS SRAM
9/20/06, v 2.0Alliance MemoryP. 1 of 10
®
Features
Industrial (-40
o
to 85
o
C) temperature
Organization: 65,536 words × 16 bits
Cente
r power and ground pins for low noise
High s
peed
- 12 ns a
ddress access time
- 6 ns outp
ut enable access time
Low po
wer consumption via chip deselect
Upper
and Lower byte pin
Easy memory expansion with
CE, OE inputs
TTL-compatible, three-state I/O
JEDEC
standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
- 48
-ball 7 × 7 mm BGA
ESD protection ? 2000 volts
Logic block diagram
65,536 × 16
Array
OE
CE
WE
Address decoder
redoced sserddA
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
8A
9A
01A
11A
21A
31A
41A
51A
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/
O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A
9
A10
A
11
NC
A0
C
E
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
C62013C7SA
Pin arrangement
0000048 - BGA Ball-Grid-Array Package
1 2 3 4 5 6
A LB
OE A
0
A
1
A
2
NC
B I/O8 UB
A3 A4 CE I/O0
C I/O9
I/O10
A5 A6 I/O1 I/O2
D V
SS
I/O11
NC A7 I/O3 V
DD
E V
DD
I/O12
NC NC I/O4 V
SS
F I/O14
I/O13
A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE
I/O7
H NC A8 A9 A10 A11 NC
AS7C31026C
9/20/06, v 2.0Alliance MemoryP. 2 of 10
®
Functional description
The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are de
sired.
Equal address access
and cycle times (t
AA
, t
RC
, t
WC
) of 12 ns with output enable access times (t
OE
) of 6 ns are ideal for high-
performance applications.
When CE
is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE
). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle
2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable
(OE
) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE
) and chip enable (CE) with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable
is active, output drivers stay in high-impedance mode.
The devi
ce provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
writte
n and read. LB
controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in
common
industry standard packages
.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to abs
olute maximum rating conditions for extended periods may affect reliability.
Key: H = high, L = low, X = don’t care.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
CC
relative to GND V
t1
–0.50 +4.60 V
Voltage on any pin relative to GND V
t2
–0.50 V
CC
+0.50 V
Power dissipation P
D
1.25 W
Storage temperature (plastic) T
stg
–55 +125 °C
Ambient temperature with VCC applied T
bias
–55 +125 °C
DC current into outputs (low) I
OUT
50 mA
Truth table
CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode
H X X X X High Z High Z Standby (I
SB
), I
SBI
)
L H L L H D
OUT
High Z Read I/O0–I/O7 (I
CC
)
L H L H L High Z D
OUT
Read I/O8–I/O15 (I
CC)
L H L L L D
OUT
D
OUT
Read I/O0–I/O15 (I
CC
)
L L X L L D
IN
D
IN
Write I/O0–I/O15 (I
CC
)
L L X L H D
IN
High Z Write I/O0–I/O7 (I
CC
)
L L X H L High Z D
IN
Write I/O8–I/O15 (I
CC
)
L
L
H
X
H
X
X
H
X
H
High Z High Z Output disable (I
CC
)
9/20/06, v 2.0Alliance MemoryP. 3 of 10
®
V
IL
= -2.0V for pulse width less than 5ns, once per cycle.
V
IH =
V
CC
+2.0V for pulse width less than 5ns, once per cycle.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage V
CC
3.0 3.3 3.6 V
Input voltage V
IH
2.0 V
CC
+ 0.5 V
V
IL
–0.5 0.8 V
Ambient operating temperature (industrial) T
A
–40 85
o
C
DC operating characteristics (over the operating range)
1
Parameter Sym Test conditions
AS7C31026C-12
UnitMin Max
Input leakage current | I
LI
|
V
CC
= Max
V
IN
= GND to V
CC
5 µA
Output leakage current | I
LO
|
V
CC
= Max
CE
= V
IH
,
V
OUT
= GND to V
CC
5 µA
Operating power supply current I
CC
V
CC
= Max,
CE
? V
IL
, I
OUT
= 0mA
f = f
Max
160 mA
Standby power supply current
I
SB
V
CC
= Max,
CE
? V
IH
, f = f
Max
45
mA
I
SB1
V
CC
= Max, CE ? V
CC
–0.2 V,
V
IN
? 0.2 V or
V
IN
? V
CC
–0.2 V, f = 0
10
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min 0.4 V
V
OH
I
OH
= –4 mA, V
CC
= Min 2.4 V
Capacitance (f = 1MHz, T
a
= 25 °C, V
CC
= NOMINAL)
2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
IN
A, CE, WE, OE, LB, UB V
IN
= 0 V 6 pF
I/O capacitance C
I/O
I/O V
IN
= V
OUT
= 0 V 7 pF
Note:
1. This parameter is guaranteed by device characterization, but is not production tested.
AS7C31026C

AS7C31026C-12TINTR

Mfr. #:
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 3.3V, 12ns, FAST 64K x 16 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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