Operation STM1061
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3 Operation
3.1 Output
The STM1061 Voltage Detector monitors system voltages from 1.6 to 5V in 100mV
increments. The detector is designed to ignore fast transients on V
CC
and has a voltage
hysteresis (V
HYST
). The STM1061 asserts an output signal (OUT) whenever V
CC
goes
below the Voltage Detect Threshold (V
TH–
). The output signal (OUT) stays asserted until
V
CC
goes above the Voltage Detect Release (V
TH+
). Output voltage (V
OUT
) is guaranteed
valid down to V
CC
=0.7V at 25°C.
The STM1061has an open drain active-low output which will sink current when output is
asserted. Connect a pull-up resistor from OUT
to any supply voltage up to 6V (see Figure 6
on page 6). Select a resistor value large enough to register a logic low, and small enough to
register a logic high while all of the input current and leakage paths connected to the reset
output line are being supplied. A 10k pull-up is sufficient in most applications.
The advantages of open drain output is the ability to connect more open drain outputs in
parallel (wired OR connections) as well as connect the output to a power supply voltage
different from V
CC
.
3.2 Negative-Going V
CC
Transients and Undershoot
The STM1061 device is relatively immune to negative-going V
CC
transients (glitches). The
graph (see Figure 11 on page 11) indicates the maximum pulse width a negative V
CC
transient can have without causing a reset pulse. As the magnitude of the transient
increases (further below the threshold), the maximum allowable pulse width decreases. Any
combination of duration and overdrive which lies under the curve will NOT generate a reset
signal.
A 0.1µF bypass capacitor mounted as close as possible to the V
CC
pin provides additional
transient immunity.
