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AD7394ARZ-REEL7

P1-P3P4-P6P7-P9P10-P12
AD7394/AD7395
–4–
REV. 0
Table I. Control Logic Truth Table
CS CLK RS MSB SHDN LDA/B Serial Shift Register Function DAC Register Function
H X H X H H No Effect Latched
L L H X H H No Effect Latched
L H H X H H No Effect Latched
L ↑+ H X H H Shift-Register-Data Advanced One Bit Latched
L ↑+ H X H L Shift-Register-Data Advanced One Bit Transparent
L H H X H L No Effect Transparent
↑+ L H X H H No Effect Latched
HX H X H ↓– No Effect Updated with Current Shift Register
Contents
H X H X H L No Effect Transparent
X X L H H X No Effect Loaded with 800
H
XX ↑+ H H H No Effect Latched with 800
H
X X L L H X No Effect Loaded with All Zeros
XX ↑+ L H H No Effect Latched All Zeros
X X X X L X No Effect No Affect
NOTES
1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care
2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.
t
LD1
t
CSH
61 LSB
ERROR BAND
t
CLRW
t
S
t
S
t
LDW
t
CH
t
CL
t
CSS
t
LD2
t
DS
t
DH
D0D1D2D3D4D5D6D7D8D9D10D11
SDI
CLK
CS
LDA,B
SDI
CLK
FS
V
OUT
ZS
LDA,B
RS
Figure 2. Timing Diagram
t
SDR
I
DD
SHDN
Figure 3. Timing Diagram
AD7394/AD7395
–5–REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7394/AD7395 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
Thermal Resistance θ
JA
14-Lead Plastic DIP Package (N-14) . . . . . . . . . . 103°C/W
14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . 158°C/W
14-Lead Thin Shrink Surface Mount (RU-14) . . . 180°C/W
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
ORDERING GUIDE
Res Temperature Package Package
Model (LSB) Range Description Options
AD7394AN 12 –40°C to +85°C 14-Lead P-DIP N-14
AD7394AR 12 –40°C to +85°C 14-Lead SOIC R-14
AD7395AN 10 –40°C to +125°C 14-Lead P-DIP N-14
AD7395AR 10 –40°C to +125°C 14-Lead SOIC R-14
AD7395ARU 10 –40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
The AD7394/AD7395 contains 709 transistors. The die size measures 70 mil × 99 mil.
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
AD7395AR and AD7395AN Only . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
␣ ␣ N-14 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . .+300°C
␣ ␣ R-14 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ RU-14 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . .+224°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table II. AD7394 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7394 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table III. AD7395 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB LSB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7395 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AD7394/AD7395
–6–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Function
1 AGND Analog Ground.
2V
OUTA
DAC A Voltage Output.
3V
REF
DAC Reference voltage input terminal. Establishes DAC full-scale output voltage. Pin can be tied to V
DD
pin.
4 DGND Digital Ground. Should be tied to analog GND.
5 CS Chip Select, active low input. Disables shift register loading when high. Does not effect LDA or LDB operation.
6 CLK Clock input, positive edge clocks data into shift register, MSB data bit first.
7 SDI Serial Data Input, input data loads directly into the shift register.
8 LDA Load DAC register strobe, level sensitive active low. Transfers shift register data to DAC A register. Asyn-
chronous active low input. See Control Logic Truth Table for operation.
9 RS Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active
low input.
10 LDB Load DAC register strobe, level-sensitive active low. Transfers shift register data to DAC B register. Asyn-
chronous active low input. See Control Logic Truth Table for operation.
11 MSB Digital Input: Logic High presets DAC registers to half-scale 800
H
(sets MSB bit to one) when the RS pin is
strobed; Logic Low clears all DAC registers to zero (000
H
) when the RS pin is strobed.
12 SHDN Active low shutdown control input. Does not affect register contents as long as power is present on V
DD
. New
data can be loaded into the shift register and DAC register during shutdown. When device is powered up the
most recent data loaded into the DAC register will control the DAC output.
13 V
DD
Positive power supply input. Specified range of operation +2.7 V to +5.5 V
14 V
OUTB
DAC B Voltage Output.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AGND
V
OUTA
V
REF
DGND
CS
CLK
SDI
V
OUTB
V
DD
SHDN
MSB
LDB
RS
LDA
AD7394
AD7395
P1-P3P4-P6P7-P9P10-P12

AD7394ARZ-REEL7

Mfr. #:
Buy AD7394ARZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
IC DAC 12BIT SERIAL 3V 14SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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