AD7394ARZ-REEL7

AD7394/AD7395
–7–REV. 0
CODE – Decimal
1.5
–1.5
0 1000500
INL – LSB
0
–0.5
0.5
1
–1
1500 25002000 3000 40003500
T
A
= +258C, +858C
V
DD
= 3V
V
REF
= 2.5V
T
A
= –558C
Figure 4. AD7394 Integral Nonlinear-
ity Error vs. Code
TEMPCO – ppm/8C
FREQUENCY
35
0
40
30
20
15
10
5
25
26 3828 30 32 34 36
SS = 200,
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= +858C TO –408C
AD7395
Figure 7. Full-Scale Output Tempco
Histogram
FREQUENCY – Hz
OUTPUT NOISE DENSITY – mV/ Hz
10
8
0
1 10 100k
V
DD
= 5V
V
REF
= 2.5V
T
A
= +258C
100 1k 10k
6
4
2
Figure 10. AD7394 Output Noise
Density vs. Frequency
Typical Performance Characteristics–
TOTAL UNADJUSTED ERROR – LSB
25
20
0
FREQUENCY
15
10
5
23 22 21
01
SS = 200 UNITS
T
A
= +258C
V
DD
= 2.7V
V
REF
= 2.5V
AD7394
Figure 5. Total Unadjusted Error
Histogram
V
REF
– Volts
INL – LSB
0.6
0.3
0
0 0.5 5
1 1.5 2 2.5 3 3.5 4 4.5
0.5
0.4
0.2
0.1
V
DD
= 5.0V
T
A
= +258C
CODE = 768
H
AD7394
Figure 8. Integral Nonlinearity Error
vs. V
REF
V
IN
– Volts
I
DD
mA
140
100
135
120
115
110
105
130
125
0 0.5 3
1 1.5 2 2.5
V
DD
= 3V
V
IN
3V TO 0V
V
IN
0V TO 3V
AD7394
Figure 11. Supply Current vs. Logic
Input Voltage
TOTAL UNAJUSTED ERROR – LSB
FREQEUENCY
50
40
0
–5
0
51015
30
20
10
SS = 200 UNITS
T
A
= +258C
V
DD
= 2.7V
V
REF
= 2.5V
AD7395
Figure 6. Total Unadjusted Error
Histogram
V
REF
– Volts
0
0.5 5
1 1.5 2 2.5 3 3.5 4 4.5
FSE – LSB
30
25
215
5
0
25
210
20
10
15
T
A
= +258C
TOTAL UNADJUSTED
FULL SCALE ERROR
FULL SCALE ERROR
AD7394
Figure 9. Full-Scale Error vs. V
REF
V
DD
– Volts
LOGIC THRESHOLD – V
5
4.5
1
23 7
456
3
2.5
2
1.5
4
3.5
V
LOGIC
FROM LOW TO HIGH
V
LOGIC
FROM HIGH TO LOW
AD7394
Figure 12. Logic Threshold vs. Sup-
ply Voltage
AD7394/AD7395
–8–
REV. 0
CLOCK FREQUENCY – Hz
I
DD
mA
1800
1600
0
1k 10k 10M
100k 1M
800
600
400
200
1400
1200
1000
A: I
DD
= 2.7V, CODE = 555
H
B: I
DD
= 2.7V, CODE = 3FF
H
C: V
DD
= 5.5V, CODE = 155
H
D: V
DD
= 5.5V, CODE = 3FF
H
A
D
C
B
AD7394
Figure 13. Supply Current vs. Clock
Frequency
D V
OUT
– LSB
CURRENT SOURCING – mA
10
3
0
210 29
0
28 27 26 25 24 23 22 21
9
4
2
1
6
5
8
7
V
DD
= 5V
V
DD
= 3V
V
REF
= 2.5V
CODE = 800
H
Figure 16. AD7394 I
OUT
Source Cur-
rent vs.
V
OUT
HOURS OF OPERATION – 1508C
NOMINAL CHANGE IN V
OUT
– mV
1.4
0
0 100 600
200 300 400 500
1.2
1
0.8
0.4
0.2
0.6
CODE = 000
H
CODE = FFF
H
AD7394
Figure 19. Long-Term Drift Acceler-
ated by Burn-In
FREQUENCY – Hz
PSRR – dB
80
70
0
1 10 10k
100 1k
40
30
20
10
60
50
V
DD
= 5.0V, 65%
V
DD
= 3.0V, 65%
T
A
= +258C
Figure 14. AD7394 Power Supply
Rejection vs. Frequency
TIME – 2ms/DIV
V
OUT
– Volts
1.262
1.257
1.237
1.252
1.247
1.242
V
DD
= +5V
V
REF
= 2.5V
T
A
= +258C
CODE = 800
H
TO 7FF
H
5mV/DIV
Figure 17. Midscale Transition
Performance
D V
OUT
– LSB
CURRENT SINKING – mA
20
6
0
01 10
23 4 567 89
18
8
4
2
12
10
16
14
V
DD
= 3V
V
DD
= 5V
V
REF
= 2.5V
CODE = 800
H
Figure 15. AD7394 I
OUT
Sink Current
vs.
V
OUT
GAIN – dB
0
25
250
100 1k
V
DD
= 5V
CODE = FFF
H
10k 100k
230
235
240
245
210
215
220
225
FREQUENCY – Hz
Figure 18. AD7395 Reference Multi-
plying Bandwidth
AD7394/AD7395
–9–REV. 0
OPERATION
The AD7394 and AD7395 are a set of pin compatible, dual,
12-bit/10-bit digital-to-analog converters. These single-supply
operation devices consume less than 200 microamps of current
while operating from power supplies in the +2.7 V to +5.5 V
range, making them ideal for battery operated applications.
They contain a voltage-switched, 12-bit/10-bit, laser trimmed
digital-to-analog converter, rail-to-rail output op amps, two
DAC registers and a serial input shift register. The external
reference input has constant input resistance independent of the
digital code setting of the DAC. In addition, the reference input
can be tied to the same supply voltage as V
DD
, resulting in a
maximum output voltage span of 0 to V
DD
. The serial interface
consists of a serial data input (SDI), clock (CLK) and chip
select pin (CS) and two load DAC Register pins (LDA and
LDB). A reset (RS) pin is available to reset the DAC register to
zero scale or midscale, depending on the digital level applied to
the MSB pin. This function is useful for power-on reset or
system failure recovery to a known state. Additional power
savings are accomplished by activating the SHDN pin resulting
in a 1.5 µA maximum consumption sleep mode.
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
V
OUT
=
V
REF
× D
2
N
(1)
where D is the decimal data word loaded into the DAC register
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7395 using a 2.5 V reference, Equation 1 simpli-
fies to:
V
OUT
=
2.5 × D
1024
(2)
Using Equation 2 the nominal midscale voltage at V
OUT
is
1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step
size is = 2.5 × 1/1024 = 0.0024 V.
For the 12-bit AD7394 operating from a 5.0 V reference Equa-
tion 1 becomes:
V
OUT
=
5.0 × D
4096
(3)
Using Equation 3 the AD7394 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of
4.998 V. The LSB step size is = 5.0 × 1/4096 = 0.0012 V.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision perfor-
mance while operating near either power supply. Figure 20
shows an equivalent output schematic of the rail-to-rail-ampli-
fier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
N-CH
V
DD
V
OUT
AGND
P-CH
Figure 20. Equivalent Analog Output Circuit
The rail-to-rail output stage provides more than ±1 mA of out-
put current. The N-channel output pull-down MOSFET shown
in Figure 20 has a 35 ON resistance, which sets the sink cur-
rent capability near ground. In addition to resistive load driving
capability, the amplifier has also been carefully designed and
characterized for up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input resistance
independent of digital code which results in reduced glitches on
the external reference voltage source. The high 2.5 M input
resistance minimizes power dissipation within the AD7394/
AD7395 D/A converters. The V
REF
input accepts input voltages
ranging from ground to the positive supply voltage V
DD
. One of
the simplest applications, which saves an external reference
voltage source, is connection of the V
REF
terminal to the positive
V
DD
supply. This connection results in a rail-to-rail voltage
output span maximizing the programmed range. The reference
input will accept ac signals as long as they are kept within the
supply voltage range, 0 < V
REF
< V
DD
. The reference bandwidth
and integral nonlinearity error performance are plotted in the
Typical Performance Characteristics section (see Figures 8 and
18). The ratiometric reference feature makes the AD7394/AD7395
an ideal companion to ratiometric analog-to-digital converters
such as the AD7896.

AD7394ARZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC DAC 12BIT SERIAL 3V 14SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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