6
FN8247.8
May 10, 2012
Principles of Operation
The ISL90727 and ISL90728 are integrated circuits
incorporating one DCP with its associated registers and an
I
2
C serial interface providing direct communication between
a host and the potentiometer.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
pins). The R
W
pin of the DCP is
connected to intermediate nodes, and is equivalent to the wiper
terminal of a mechanical potentiometer. The position of the
wiper terminal within the DCP is controlled by a 7-bit volatile
Wiper Register (WR). The DCP has its own WR. When the WR
of the DCP contains all zeroes (WR<6:0> = 00h), its wiper
terminal (R
W
) is closest to its “Low” terminal (R
L
). When the
WR of the DCP contains all ones (WR<6:0> = 7Fh), its wiper
terminal (R
W
) is closest to its “High” terminal (R
H
). As the value
of the WR increases from all zeroes (00h) to all ones (127
decimal), the wiper moves monotonically from the position
closest to R
L
to the position closest to R
H
. At the same time,
the resistance between R
W
and R
L
increases monotonically,
while the resistance between R
H
and R
W
decreases
monotonically. R
L
is connected to the GND pin of the device, so
the wiper movement will always be relative to R
L
.
While the ISL90727 and ISL90728 are being powered up,
the WR is reset to 40h (64 decimal), which locates R
W
roughly at the center between R
L
and R
H
.
The WR and IVR can be read or written directly using the
I
2
C serial interface as described in the following sections.
I
2
C Serial Interface
The ISL90727 and ISL90728 support bidirectional bus
oriented protocol. The protocol defines any device that
sends data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the transfer is
a master and the device being controlled is the slave. The
master always initiates data transfers and provides the clock
for both transmit and receive operations. Therefore, the
ISL90727 and ISL90728 operate as slave devices in all
applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 1). On power-up of the ISL90727 and ISL90728, the
SDA pin is in the input mode.
All I
2
C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH.
The ISL90727 and ISL90728 continuously monitor the SDA
and SCL lines for the START condition and do not respond to
any command until this condition is met (see Figure 1). A
START condition is ignored during the power-up sequence and
during internal non-volatile write cycles.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 1).
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
eight bits of data (see Figure 2).
The ISL90727 and ISL90728 respond with an ACK after
recognition of a START condition followed by a valid
Identification Byte, and once again after successful receipt of
an Address Byte. The ISL90727 and ISL90728 also respond
with an ACK after receiving a Data Byte of a write operation.
The master must respond with an ACK after receiving a Data
Byte of a read operation.
A valid Identification Byte contains 0101110 as the seven
MSBs for the ISL90727 and 0111110 as the seven MSBs for
the ISL90728. The LSB in the Read/Write
bit. Its value is “1”
for a Read operation, and “0” for a Write operation (see
Table 1).
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90727 and ISL90728 respond with an ACK. At this time,
the device enters its standby state (see Figure 3).
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection of both volatile and
non-volatile registers. During a Write sequence, the Data
Byte is loaded into an internal shift register as it is received.
If the Address Byte is 0, the Data Byte is transferred to the
Wiper Register (WR) at the falling edge of the SCL pulse
that loads the last bit (LSB) of the Data Byte. If an address
other than 00h or an invalid slave address is sent, then the
device will respond with no ACK.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 4). The master
initiates the operation issuing the following sequence: a
TABLE 1. IDENTIFICATION BYTE FORMAT
ISL90727 0 1 0 1 1 1 0 R/W
ISL90728 0 1 1 1 1 1 0 R/W
MSB LSB
ISL90727, ISL90728
