ISL90728WIE627Z-T7A

7
FN8247.8
May 10, 2012
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W
bit set to “1”. After each of the three bytes,
the ISL90727 and ISL90728 respond with an ACK. Then the
ISL90727 and ISL90728 transmit the Data Byte as long as
the master responds with an ACK during the SCL cycle
following the eighth bit of each byte. The master then
terminates the read operation (issuing a STOP condition)
following the last bit of the Data Byte (see Figure 4).
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
FIGURE 1. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE 3. BYTE WRITE SEQUENCE (ISL90727 VERSION SHOWN)
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL23711
A
C
K
0
0
011
A
C
K
WRITE
SIGNAL AT SDA
0000011000000
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W
= 0
ADDRESS
BYTE
A
C
K
A
C
K
00011
S
T
O
P
0
1
011
IDENTIFICATION
BYTE WITH
R/W
= 1
A
C
K
S
T
A
R
T
DATA BYTE
110 0000 00
110
00
FIGURE 4. READ SEQUENCE (ISL90727 VERSION SHOWN)
ISL90727, ISL90728
8
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8247.8
May 10, 2012
ISL90727, ISL90728
Small Outline Transistor Plastic Packages (SC70-6)
D
e1
E
C
L
e
b
C
L
A2
A
A1
C
L
0.20 (0.008)
M
0.10 (0.004) C
C
-C-
SEATING
PLANE
123
456
E1
C
L
C
VIEW C
VIEW C
L
R1
R
4X θ1
4X θ1
GAUGE PLANE
L1
SEATING
α
L2
C
PLANE
c
BASE METAL
WITH
c1
b1
PLATING
b
PIN 1
INDEX AREA
8
P6.049
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.031 0.043 0.80 1.10 -
A1 0.000 0.004 0.00 0.10 -
A2 0.031 0.039 0.00 1.00 -
b 0.006 0.012 0.15 0.30 -
b1 0.006 0.010 0.15 0.25
c 0.003 0.009 0.08 0.22 6
c1 0.003 0.009 0.08 0.20 6
D 0.073 0.085 1.85 2.15 3
E 0.071 0.094 1.80 2.40 -
E1 0.045 0.053 1.15 1.35 3
e 0.0256 Ref 0.65 Ref -
e1 0.0512 Ref 1.30 Ref -
L 0.010 0.018 0.26 0.46 4
L1 0.017 Ref. 0.420 Ref.
L2 0.006 BSC 0.15 BSC
N 665
R 0.004 - 0.10 -
R1 0.004 0.010 0.15 0.25
α
0
o
8
o
0
o
8
o
-
Rev. 3 4/12
NOTES:
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO203AB.
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
8. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

ISL90728WIE627Z-T7A

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs 6LD SC70 SINGLE VOLATILE 128 TAP DCP
Lifecycle:
New from this manufacturer.
Delivery:
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