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AD974BRS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
REV. A
AD974
–15–
OFFSET AND GAIN ADJUSTMENT
The AD974 is factory trimmed to minimize gain, offset and
linearity errors. There are no internal provisions to allow for any
further adjustment of offset error through external circuitry.
The reference of the AD974 can be adjusted as shown in Figure
12. This will allow the full-scale error of any one channel to be
adjusted to zero or will allow the average full-scale error of the
four channels to be minimized.
2.2mF
2.2mF
576kV
50kV
+
+
CAP
REF
AGND2
AD974
+5V
Figure 12. AD974 Full-Scale Trim
VOLTAGE REFERENCE
The AD974 has an on-chip temperature compensated bandgap
voltage reference that is factory trimmed to +2.5 V ± 20␣ mV.
The accuracy of the AD974 over the specified temperature
range is dominated by the drift performance of the voltage refer-
ence. The on-chip voltage reference is laser-trimmed to provide
a typical drift of 7␣ ppm/°C. This typical drift characteristic is
shown in Figure 13, which is a plot of the change in reference
voltage (in mV) versus the change in temperature—notice the
plot is normalized for zero error at +25°C. If improved drift perfor-
mance is required, an external reference such as the AD780
should be used to provide a drift as low as 3 ppm/°C. In order to
simplify the drive requirements of the voltage reference (internal
or external), an on-chip reference buffer is provided.
–55 25
125
1mV/DIV
DEGREES – Celsius
Figure 13. Reference Drift
The output of this buffer is provided at the CAP pin and is
available to the user; however, when externally loading the refer-
ence buffer, it is important to make sure that proper precautions
are taken to minimize any degradation in the ADC’s perfor-
mance. Figure 14 shows the load regulation of the reference
buffer. Notice that this figure is also normalized so that there is
zero error with no dc load. In the linear region, the output imped-
ance at this point is typically 1 Ω. Because of this output imped-
ance, it is important to minimize any ac- or input-dependent
loads that will lead to increased distortion. Any dc load will
simply act as a gain error. Although the typical characteristic of
Figure 14 shows that the AD974 is capable of driving loads
greater than 15 mA, it is recommended that the steady state
current not exceed 2 mA.
LOAD CURRENT – 5mA/DIV
SOURCE CAPABILITY SINK CAPABILITY
dV ON CAP PIN – 10nV/DIV
Figure 14. CAP Pin Load Regulation
Using an External Reference
In addition to the on-chip reference, an external 2.5␣ V reference
can be applied. When choosing an external reference for a
16-bit application, however, careful attention should be paid to
noise and temperature drift. These critical specifications can
have a significant effect on the ADC performance.
Figure 15 shows the AD974 used in bipolar mode with the
AD780 voltage reference applied to the REF pin. The AD780
is a bandgap reference that exhibits ultralow drift, low initial
error and low output noise. For low power applications, the
AD780 provides a low quiescent current, high accuracy and low
temperature drift solution.
BIP
VxA
VxB
AGND1
CAP
REF
AGND2
AD974
V
IN
C4
0.1mF
C2
2.2mF
+
V
ANA
TEMP V
OUT
GND
V
IN
AD780
6
4
2
3
C1
2.2mF
+
–
C3
1mF
+
–
+5V
0.1mF
–
Figure 15. External Reference to AD974 Configured for
±
10 V Input Range
REV. A
AD974
–16–
AC PERFORMANCE
The AD974 is fully specified and tested for dynamic perfor-
mance specifications. The ac parameters are required for signal
processing applications such as speech recognition and spectrum
analysis. These applications require information on the ADC’s
effect on the spectral content of the input signal. Hence, the
parameters for which the AD974 is specified include S/(N+D),
THD and Spurious Free Dynamic Range. These terms are
discussed in greater detail in the following sections.
As a general rule, it is recommended that the results from sev-
eral conversions be averaged to reduce the effects of noise and
thus improve parameters such as S/(N+D) and THD. AC per-
formance can be optimized by operating the ADC at its maxi-
mum sampling rate of 200 kHz and digitally filtering the resulting
bit stream to the desired signal bandwidth. By distributing noise
over a wider frequency range the noise density in the frequency
band of interest can be reduced. For example, if the required
input bandwidth is 50 kHz, the AD974 could be oversampled
by a factor of 4. This would yield a 6 dB improvement in the
effective SNR performance.
FREQUENCY – kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–125
0 102030405060708090100
AMPLITUDE – dB
515 253545556575 8595
5280 POINT FFT
f
SAMPLE
= 200kHz
f
IN
= 20kHz
SNRD = 86.7dB
THD = 100.7dB
Figure 16. FFT Plot
DC PERFORMANCE
The factory calibration scheme used for the AD974 compen-
sates for bit weight errors that may exist in the capacitor array.
The mismatch in capacitor values is adjusted (using the calibra-
tion coefficients) during a conversion, resulting in excellent dc
linearity performance. Figures 17 and 18, respectively, show
typical INL and DNL plots for the AD974 at +25°C.
A histogram test is a statistical method for deriving an A/D
converter’s differential nonlinearity. A ramp input is sampled
by the ADC and a large number of conversions are taken at
each voltage level, averaged and then stored. The effect of
averaging is to reduce the transition noise by 1/n. If 64 samples
are averaged at each point, the effect of transition noise is
reduced by a factor of 8; i.e., a transition noise of 0.8 LSBs rms
is reduced to 0.1 LSBs rms. Theoretically the codes, during a
test of DNL, would all be the same size and therefore have an
equal number of occurrences. A code with an average number
of occurrences would have a DNL of “0.” A code that is
different from the average would have a DNL that was either
greater or less than zero LSB. A DNL of –1 LSB indicates that
there is a missing code present at the 16-bit level and that the
ADC exhibits 15-bit performance.
SAMPLES – K
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0 5 10 15 20 25 30 35 40 45 50 55 60 66
100%
Figure 17. INL Plot
SAMPLES – K
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0 5 10 15 20 25 30 35 40 45 50 55 60 66
100%
Figure 18. DNL Plot
INPUT SIGNAL FREQUENCY – kHz
90
1 100010010
80
70
60
50
40
30
20
10
SNR+D (dB) FOR AD974
SINAD (dB) FOR V
IN
= 0dB
Figure 19. S/(N+D) vs. Input Frequency
REV. A
AD974
–17–
TEMPERATURE – 8C
110
80
–75 150–50 –25
0
25 50 75 100 125
105
100
95
90
85
–80
–110
–85
–90
–95
–100
–105
SFDR, S/N + D – dB
SNRD
SFDR
THD
THD – dB
Figure 20. AC Parameters vs. Temperature
DC CODE UNCERTAINTY
Ideally, a fixed dc input should result in the same output code
for repetitive conversions; however, as a consequence of un-
avoidable circuit noise within the wideband circuits of the ADC,
a range of output codes may occur for a given input voltage.
Thus, when a dc signal is applied to the AD974 input, and
10,000 conversions are recorded, the result will be a distribution
of codes as shown in Figure 21. This histogram shows a bell
shaped curve consistent with the Gaussian nature of thermal
noise. The histogram is approximately seven codes wide. The
standard deviation of this Gaussian distribution results in a code
transition noise of 1 LSB rms.
4000
0
–3 –2 –1
0
1234
3500
2000
1500
1000
500
3000
2500
Figure 21. Histogram of 10,000 Conversions of a DC Input
POWER-DOWN FEATURE
The AD974 has analog and reference power-down capability
through the PWRD pin. When the PWRD pin is taken high,
the power consumption drops from a maximum value of
100 mW to a typical value of 50 µW. When in the power-
down mode the previous conversion results are still available in
the internal registers and can be read out providing it has not
already been shifted out.
When used with an external reference, connected to the REF
pin and a 2.2 µF capacitor, connected to the CAP pin, the
power-up recovery time is typically 1 ms. This typical value of
1 ms for recovery time depends on how much charge has de-
cayed from the external 2.2 µF capacitor on the CAP pin and
assumes that it has decayed to zero. The 1 ms recovery time has
been specified such that settling to 16 bits has been achieved.
When used with the internal reference, the dominant time con-
stant for power-up recovery is determined by the external ca-
pacitor on the REF pin and the internal 4K impedance seen at
that pin. An external 2.2 µF capacitor is recommended for the
REF pin.
CROSSTALK
The crosstalk between adjacent channels, nonadjacent channels
and worst-case adjacent channels is shown in Figures 22 to 24.
The worst-case crosstalk occurs between channels 1 and 2.
–80
–115
1 10 100 1000
–95
–100
–105
–110
–85
–90
10000
ACTIVE CHANNEL INPUT FREQUENCY – kHz
RESULTING AMPLITUDE ON SELECTED
CHANNEL (dB) WITH INPUT GROUNDED
ADJACENT CHANNELS,
WORST PAIR
NONADJACENT
CHANNELS
Figure 22. Crosstalk vs. Input Frequency (kHz)
0
–130
12
–90
–100
–110
–120
–70
–80
FREQUENCY – kHz
dBFS
4 6 8 10 12 14 16 18 20
–60
–40
–50
–30
–10
–20
Figure 23. Adjacent Channel Crosstalk, Worst Pair
(8192 Point FFT; AIN 2 = 1.02 kHz, –0.1 dB; AIN 1 = AGND)
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AD974BRS

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Analog to Digital Converters - ADC 4CH 16-Bit 200 kSPS
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