LT1738EG#PBF Datasheet LT1738EG#TRPBF, LT1738IG#TRPBF, LT1738EG#PBF | P10-P12

LT1738

1738fa

The current slew feedback loop consists of the voltage

across the external sense resistor, which is internally

amplified and differentiated. The derivative is limited to a

value set by R

CSL

. The current slew rate is thus inversely

proportional to both the value of sense resistor and R

CSL.

The two control loops are combined internally so that a

smooth transition from current slew control to voltage

slew control is obtained. When turning on, the driver

current will slew before voltage. When turning off, voltage

will slew before current. In general it is desirable to have

VSL

and R

CSL

of similar value.

Internal Regulator

Most of the control circuitry operates from an internal 2.4V

low dropout regulator that is powered from V

. The

internal low dropout design allows V

to vary from 2.7V

to 20V with stable operation of the controller. When SHDN

< 1.3V the internal regulator is completely disabled.

5V Regulator

A 5V regulator is provided for powering external circuitry.

This regulator draws current from V

and requires V

be greater than 6.5V to be in regulation. It can sink or

source 10mA. The output is current limited to prevent

against destruction from accidental short circuits.

Safety and Protection Features

There are several safety and protection features on the

chip. The first is overcurrent limit. Normally the gate driver

will go low when the output of the internal sense amplifier

exceeds the voltage on the V

pin. The V

pin is clamped

such that maximum output current is attained when the CS

pin voltage is 0.1V. At that level the outputs will be

immediately turned off (no slew). The effect of this control

is that the output voltage will foldback with overcurrent.

In addition, if the CS voltage exceeds 0.22V, the V

and SS

pins will be discharged to ground, resetting the soft-start

function. Thus if a short is present this will allow for faster

MOSFET turnoff and less MOSFET stress.

If the voltage on the FB pin exceeds regulation by approxi-

mately 0.22V, the outputs will immediately go low. The

implication is that there is an overvoltage fault.

The voltage on GCL determines two features. The first is

the maximum gate drive voltage. This will protect the

MOSFET gate from overvoltage.

With GCL tied to a zener or an external voltage source then

the maximum gate driver voltage is approximately

GCL

␣ – 0.2V. If GCL is tied to V

, then the maximum gate

voltage is determined by V

and is approximately

– 1.6V. There is an internal 19V zener on the GCL pin

that prevents the gate driver pin from exceeding approxi-

mately 19V.

In addition, the GCL voltage determines undervoltage

lockout of the gate drive. This feature disables the gate

driver if V

is too low to provide adequate voltage to turn

on the MOSFET. This is helpful during start up to insure the

MOSFET has sufficient gate drive to saturate.

If GCL is tied to a voltage source or zener less than 6.8V,

the gate driver will not turn on until V

exceeds GCL

voltage by 0.8V. For V

GCL

above 6.5V, the gate drive is

insured to be off for V

< 7.3V and it will be turned on by

GCL

+ 0.8V.

If GCL is tied to V

, the gate driver is always on

(undervoltage lockout is disabled).

The gate drive has current limits for the drive currents. If

the sink or source current is greater than 300mA then the

current will be limited.

The V5 regulator also has internal current limiting that will

only guarantee ±10mA output current.

There is also an on chip thermal shutdown circuit that will

turn off the output in the event the chip temperature rises

to dangerous levels. Thermal shutdown has hysteresis

that will cause a low frequency (<1kHz) oscillation to occur

as the chip heats up and cools down.

The chip has an undervoltage lockout feature that will

force the gate driver low in the event that V

drops below

2.5V. This insures predictable behavior during start up and

shut down. SHDN can be used in conjuction with an

external resistor divider to completely disable the part if

the input voltage is too low. This can be used to insure

adequate voltage to reliably run the converter. See the

section in Applications Information.

Table 1 summarizes these features.

OPERATIO

LT1738

1738fa

APPLICATIO S I FOR ATIO

WUU

OPERATIO

Reducing EMI from switching power supplies has tradi-

tionally invoked fear in designers. Many switchers are

designed solely on efficiency and as such produce wave-

forms filled with high frequency harmonics that then

propagate through the rest of the system.

The LT1738 provides control over two of the more impor-

tant variables for controlling EMI with switching inductive

loads: switch voltage slew rate and switch current slew

rate. The use of this part will reduce noise and EMI over

conventional switch mode controllers. Because these

variables are under control, a supply built with this part will

exhibit far less tendency to create EMI and less chance of

encountering problems during production.

It is beyond the scope of this data sheet to get into EMI

fundamentals. Application Note 70 contains much infor-

mation concerning noise in switching regulators and

should be consulted.

Oscillator Frequency

The oscillator determines the switching frequency and

therefore the fundamental positioning of all harmonics.

The use of good quality external components is important

to ensure oscillator frequency stability. The oscillator is of

a sawtooth design. A current defined by external resistor

is used to charge and discharge the capacitor C

. The

discharge rate is approximately ten times the charge rate.

By allowing the user to have control over both compo-

nents, trimming of oscillator frequency can be more easily

achieved.

The external capacitance C

is chosen by:

CnF

f kHz R k

()

()•()

Ω

2180

where f is the desired oscillator frequency in kHz. For R

equal to 16.9k, this simplifies to:

CnF

f kHz

()

129

e.g., C

= 1.29nF for f = 100kHz

Nominally R

should be 16.9k. Since it sets up current, its

temperature coefficient should be selected to compliment

the capacitor. Ideally, both should have low temperature

coefficients.

Table 1. Safety and Protection Features

FEATURE FUNCTION EFFECT on GATE DRIVER SLEW CONTROL EFFECT on V

, SS

Maximum Current Fault Turn Off FET at Maximum Immediately Goes Low Overridden None

Switch Current (V

SENSE

= 0.1)

Short-Circuit Fault Turn Off FET and Reset V

Immediately Goes Low Overridden Discharge V

, SS

for Short-Circuit (V

SENSE

= 0.22) to GND

Overvoltage Fault Turn Off Driver If FB > V

REG

+ 0.22V Immediately Goes Low Overridden None

(Output Overvoltage)

GCL Clamp Set Max Gate Voltage to Prevent Limits Max Voltage None None

FET Gate Breakdown

Gate Drive Disable Gate Drive When V

Immediately Goes Low Overridden None

Undervoltage Lockout Is Too Low. Set Via GCL Pin

Thermal Shutdown Turn Off Driver If Chip Immediately Goes Low Overridden None

Temperature Is Too Hot

Undervoltage Lockout Disable Part When V

≅ 2.55V Immediately Goes Low Overridden None

Gate Drive Source and Sink Current Limit Limit Gate Drive Current Limit Drive Current None None

V5 Source/Sink Current Limit Limit Current from V5 None None None

Shutdown Disable Part When SHDN <1.3V

LT1738

1738fa

APPLICATIO S I FOR ATIO

WUU

Oscillator frequency is important for noise reduction in

two ways. First the lower the oscillator frequency the lower

the waveform’s harmonics, making it easier to filter them.

Second the oscillator will control the placement of the

output voltage harmonics which can aid in specific prob-

lems where you might be trying to avoid a certain fre-

quency bandwidth.

Oscillator Sync

If a more precise frequency is desired (e.g., to accurately

place harmonics) the oscillator can be synchronized to an

external clock. Set the RC timing components for an

oscillator frequency 10% lower than the desired sync

frequency.

Drive the SYNC pin with a square wave (with greater than

2V amplitude). The rising edge of the sync square wave

will initiate clock discharge. The sync pulse should have a

minimum pulse width of 0.5µs.

Be careful in sync’ing to frequencies much different from

the part since the internal oscillator charge slope deter-

mines slope compensation. It would be possible to get into

subharmonic oscillation if the sync doesn’t allow for the

charge cycle of the capacitor to initiate slope compensa-

tion. In general, this will not be a problem until the sync

frequency is greater than 1.5 times the oscillator free-run

frequency.

Slew Rate Setting

The primary reason to use this part is to gain advantage of

lower EMI and noise due to the slew control. The rolloff in

higher frequency harmonics has its theoretical basis with

two primary components. First, the clock frequency sets

the fundamental positioning of harmonics and second, the

associated normal frequency rolloff of harmonics.

This part creates a second higher frequency rolloff of

harmonics that inversely depends on the slew time, the

time that voltage or current spends between the off state

and on state. This time is adjustable through the choice of

the slew resistors, the external resistors to ground on the

VSL

and R

CSL

pins and the external components used for

the external voltage feedback capacitor C

(from CAP to

the MOSFET drain) and the sense resistor. Lower slew

rates (longer slew times, lower rolloff frequency for har-

monics ) are created with higher values of R

VSL

, R

CSL

, C

and the current sense resistor.

Setting the voltage and current slew rates should be done

empirically. The most practical way of determining these

components is to set C

and the sense resistor value.

Then, start by making R

VSL

, R

CSL

each a 50k resistor pot

in series with 3.3k. Starting from the lowest resistor

setting (fast slew) adjust the pots until the noise level

meets your guidelines. Note that slower slewing wave-

forms will dissipate more power so that efficiency will

drop. You can monitor this as you make your slew adjust-

ment by measuring input and output voltage and their

respective currents. Monitor the MOSFET temperature as

slew rates are slowed. The MOSFET will heat up as

efficiency decreases.

Measuring noise should be done carefully. It is easy to

introduce noise by poor measurement techniques. Con-

sult AN70 for recommended measurement techniques.

Keeping probe ground leads very short is essential.

Usually it will be desirable to keep the voltage and current

slew resistors approximately the same. There are circum-

stances where a better optimization can be found by

adjusting each separately, but as these values are sepa-

rated further, a loss of independence of control may occur.

It is possible to use a single slew setting resistor. In this

case the R

VSL

and R

CSL

pins are tied together. A resistor

with a value of 1.8k to 34k (one half the individual resis-

tors) can then be tied from these pins to ground.

In general only the R

CSL

value will be available for adjust-

ment of current slew. The current slew time also depends

on the current sense resistor but this resistor is normally

set with consideration of the maximum current in the

MOSFET.

Setting the voltage slew also involves selection of the

capacitor C

. The voltage slew time is proportional to the

output voltage swing (basically input voltage), the external

voltage feedback capacitor and the R

VSL

value. Thus at

higher input voltages smaller capacitors will be used with

lower R

VSL

values. For a starting point use Table␣ 2.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LT1738EG#PBF

Mfr. #:

Buy LT1738EG#PBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators SR Controlled Ultralow N DC/DC Cntr

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LT1738EG#PBF

LT1738EG#PBF

Products related to this Datasheet