AMB0480A5RJ Datasheet AMB0480A5RJ8, AMB0480A5RJ | P10-P12

COMMERCIAL TEMPERATURE RANGE

IDTAMB0480

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM

PIN DESCRIPTION

Signal Type Description

Channel Interface

PN[13:0] O Northbound Output Data: High speed serial signal. Read path from AMB toward host on primary side of the DIMM connector.

PN[13:0] O Northbound Output Data Complement

SN[13:0] I Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM

connector.

SN[13:0] I Northbound Input Data Complement

PS[9:0] I Southbound Input Data: High speed serial signal. Write path from host toward AMB on primary side of the DIMM connector.

PS[9:0] I Southbound Input Data Complement

SS[9:0] O Southbound Output Data: High speed serial signal. Write path from this AMB toward next AMB on secondary side of the DIMM connector.

These output buffers are disabled for the last AMB on the channel.

SS[9:0] O Southbound Output Data Complement

FBDRES A External 100Ω precision resistor connected to VCC. On-die termination calibrated against this resistor.

DRAM Interface

CB[7:0] I/O Check bits

DQ[63:0] I/O Data

DQS[17:0] I/O Data Strobe: DDR2 data and check-bit strobe.

DQS[17:0] I/O Data Strobe Complement: DDR2 data and check-bit strobe complements.

A0A-A15A, O Address: Used for providing multiplexed row and column address to SDRAM.

A0B-A15B

BA0A-BA2A, O Bank Active: Used to select the bank within a rank.

BA0B-BA2B

RASA, RASB O Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command.

CASA, CASB O Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command.

WEA, WEB O Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command.

CS0A-CS1A, O Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are used for selecting one of two SDRAM

ranks. CS0 is used to select the first rank and CS1 is used to select the second rank.

CKE0A-CKE1A, O Clock Enable: DIMM command register enable.

CKE0B-CKE1B

ODT0A, ODT0B O DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel.

CLK[3:0] O Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are used when the AMB is configured for dual rank DIMMs.

CLK[3:0] O Clock Complement: Clocks to DRAMs.

DDR Compensation

DDRC_C14 A DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18

DDRC_B18 A DDR Compensation Ball Resistor (825Ω) connected to Compensation Common above

DDRC_C18 A DDR Compensation Ball Resistor (121Ω) connected to Compensation Common above

DDRC_B12 A DDR Compensation Ball Resistor (82Ω) connected to VSS

DDRC_C12 A DDR Compensation Ball Resistor (82Ω) connected to VDD

CS0B-CS1B

IDTAMB0480

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM

COMMERCIAL TEMPERATURE RANGE

Signal Type Description

Clocking

SCK I AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop in the AMB core. Phase Locked Loops in

the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.

SCK I AMB Clock Complement: This is the other differential reference clock input to the Phase Locked Loop in the AMB core. Phase Locked Loops

in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.

PLLTSTO O PLL Clock Observability Output: This pin can be used to observe VCO, reference clock, core clock, etc. For system debug and design

characterization.

VCCA PLL A VCC: PLL Analog Voltage for the core PLL

VSSA PLL A VSS: PLL Analog Voltage for the core PLL

System Management

SCL I/O SMBus Clock

SDA I/O SMBus Address/Data

SA[2:0] DIMM Select ID

Reset

RESET Power Good Reset

Miscellaneous Test

TEST (4 pins) NC Pin for debug and test. Must be floated on DIMM.

TESTLO (5 pins) A Pin for debug and test. Must be tied to Ground on DIMM

TESTLO_AB20 A Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS.

TESTLO_AC20 A Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS.

Power Supplies

VCC (24 pins) A 1.5V nominal supply for core I/O

VCCFBD (8 pins) A 1.5V nominal supply for FBD high speed I/O

VDD (24 pins) A 1.8V nominal supply for DDR I/O

VSS (156 pins) A Ground

VDDSPD A 3.3V nominal supply for SMB receivers and ESD diodes

Other Pins

BFUNC I Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FBDIMM. When BFUNC = 1, AMB is used as either a repeater

or a buffer for LAI function. On FB-DIMM, BFUNC is tied to Ground

RFU (18 pins) NC Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved for forwarded clocks in future AMB

implementations.

Other No Connect Pins

NC (129 pins) NC No Connect pins

PIN DESCRIPTION (CONT.)

COMMERCIAL TEMPERATURE RANGE

IDTAMB0480

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM

Symbol Description Min Max Unit

VDD Supply voltage DRAM Interface -0.5 +2.3 V

IN (DDR2). Voltage on any DDR2 interface 0.5 +2.3 V

VOUT (DDR2) pin relative to Vss

(2)

IINK Input Clamp Current +30 mA

(VIN < 0 or VIN > VDD)

OUTK Output Clamp Current +30 mA

(VOUT < 0 or VOUT > VDD)

OUT Continous Output Current +30 mA

(VOUT = 0 to VDD)

N/A Continuous current through +100 mA

each VDD or GND

CC Supply voltage for Core -0.3 +1.75 V

and High Speed Interface

TJ Junction Temperature +125 ° C

STG Storage Temperature Range –55 +100 ° C

ABSOLUTE MAXIMUM RATINGS

(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed. This value is limited to 2.3V maximum.

ADVANCED MEMORY BUFFER

NORMAL MODE DC ELECTRICAL

PARAMETERS

Parameter Min Typ Max Unit

VCC link / core

(1,2,3,4)

1.425 1.5 1.59 V

VDD 1.7 1.8 1.9 V

VDDSPD 3.0 3.3 3.6 V

NOTES:

1. AMB 1.5V voltage regulation as measured at the package Balls.

2. DC defined as 0 KHz to 30 KHz.

3. DC + AC specified as 1.5V +6%, -5% 30KHz to 1 MHz.

4. There is also a +7%, -5% tolerance allowed for current load steps associated with

initialization/error-recovery state transitions, such as into and out of EI, IBIST, and

MEMBIST. For these transitions, a temporary voltage overshoot is expected and

acceptable as long as it is within +7% (step transition for 20μs and maximum duty cycle

of 10

-6

%). Transitions between Active and Idle states are not included in this +7%,

-5% tolerance.

ELECTRICAL, POWER, AND THERMAL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

AMB0480A5RJ

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