HSMP-4810-BLKG

4
Microstrip Series Connection for HSMP-481x Series
In order to take full advantage of the low inductance of the
HSMP-481x series when using them in series applications,
both lead 1 and lead 2 should be connected together, as
shown in Figure 7.
Microstrip Shunt Connections for HSMP-481x Series
In Figure 8, the center conductor of the microstrip
line is interrupted and leads 1 and 2 of the HSMP-481x
series diode are placed across the resulting gap. This forces
the 1.5 nH lead inductance of leads 1 and 2 to appear as
part of a low pass filter, reducing the shunt
parasitic inductance and increasing the maximum available
attenuation. The 0.3 nHof shunt inductance external to the
diode is created by the via holes, and is a good estimate
for 0.032" thick material.
Typical Applications for HSMP-481x Low Inductance Series
12
3
HSMP-481x
Figure 6. Internal Connections.
Figure 7. Circuit Layout.
Figure 8. Circuit Layout.
Figure 9. Equivalent Circuit.
50 OHM MICROSTRIP LINES
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
0.3 nH
0.3 nH
0.3 pFR
j
1.5 nH 1.5 nH
R
j
0.08
+ 2.5
I
b
0.9
5
Typical Applications for HSMP-481x Low Inductance Series (continued)
Co-Planar Waveguid
e
Groundplane
Center Conductor
Groundplane
0.3 pF
0.75 nH
R
j
Equivalent Circuit Model
HSMP-381x Chip*
Co-Planar Waveguide Shunt Connection for HSMP-481x
Series
Co-Planar waveguide, with ground on the top side of the
printed circuit board, is shown in Figure 10. Since it elimi-
nates the need for via holes to ground, it offers lower shunt
parasitic inductance and higher maximum attenuation
when compared to microstrip circuit.
Figure 10. Circuit Layout.
Figure 11. Equivalent Circuit.
0.18 pF*
* Measured at -20 V
2.5
Ω
R
j
R
s
C
j
R
T
= 2.5 + R
j
C
T
= C
P
+ C
j
I
= Forward Bias Current in mA
*See AN1124 for package models.
R
j
=
80
I
0.9
Ω
6
Assembly Information
SOT-323 PCB Footprint
A recommended PCB pad layout for the miniature SOT-323
(SC-70) package is shown in Figure 12 (dimensions are in
inches). This layout provides ample allowance for package
placement by automated assembly equipment without
adding parasitics that could impair the performance.
SMT Assembly
Reliable assembly of surface mount components is a
complex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reflow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
SOT-323/-23 package, will reach solder reflow tempera-
tures faster than those with a greater mass.
After ramping up from room temperature, the circuit board
with components attached to it (held in place with solder
paste) passes through one or more preheat zones. The
preheat zones increase the temperature of the board and
components to prevent thermal shock and begin evaporat-
ing solvents from the solder paste. The reflow zone briefly
elevates the temperature sufficiently to produce a reflow
of the solder.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to components
due to thermal shock. The maximum temperature in the
reflow zone (T
MAX
) should not exceed 260°C.
These parameters are typical for a surface mount assembly
process for Avago diodes. As a general guideline, the circuit
board and components should be exposed only to the
minimum temperatures and times necessary to achieve a
uniform reflow of solder.
0.026
0.039
0.079
0.022
Dimensions in inches
0.039
1
0.039
1
0.079
2.0
0.031
0.8
Dimensions in
inches
mm
0.035
0.9
Figure 12. Recommended PCB Pad Layout
for Avago’s SC70 3L/SOT-323 Products.
Figure 13. Recommended PCB Pad Layout for Avago’s SOT-23 Products.
SOT-23 PCB Footprint

HSMP-4810-BLKG

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
PIN Diodes 100 VBR 0.35 pF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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