PI6C182AHEX

1
PS8165G 11/13/08
1
2
3
V
SS0
4
V
DD1
5
SDRAM1
6
SDRAM3 7
V
SS1
8
SDRAM2
9
V
DD2
10
11
12
13
14
V
DD5
SDRAM6
V
SS5
SDRAM5
SDRAM4
V
SS4
OE
V
DD3
SDRAM9
V
SS3
V
SSIIC
SCLOCK
27
28
26
25
24
23
22
21
20
19
18
17
16
15
V
DD0
SDRAM0
BUF_IN
SDRAM8
V
SS2
SDATA
V
DDIIC
V
DD4
SDRAM7
Diagram
Description
The PI6C182 is a high-speed low-noise 1-to-10 noninverting buf-
fer designed for SDRAM clock buffer applications, supporting
frequencies up to 110 MHz.
At power up all SDRAM output are enabled and active. The I
2
C
serial control may be used to individually activate/de ac ti vate any
driver.
The output enable pin (OE) may be pulled LOW to tri-state all
outputs.
Note:
Purchases of I
2
C components from Pericom conveys a license of
use in I
2
C system de ned by Philips Semiconductor.
Features
Low noise non-inverting 1-to-10 buffer
• Supports frequency up to 125 MHz (PI6C182A)
• Supports up to four SDRAM DIMMs
Low skew (<200ps) between any two output clocks
• I
2
C Serial Con guration interface
• Multiple V
DD
and V
SS
pins for noise reduction
3.3V power supply voltage
Separate Hi-Z state pin for testing
Packaging (Pb-free & Green available):
— 28-pin SSOP (H)
Pin Con g u ra tion
Precision 1-to-10 Clock Buffer
PI6C182
PI6C182A
SDRAM9
SDRAM2
SDRAM1
SDRAM0
BUF_IN
SDATA
OE
SCLOCK
SDRAM3
I
2
C
I/O
08-0298
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
2
PS8165G 11/13/08
Pin Description
Pin Symbol Type Qty Description
2, 3, 6, 7 SDRAM[0-3] O 4 SDRAM Byte 0 clock output
22, 23, 26, 27 SDRAM[4-7] O 4 SDRAM Byte 1 clock output
11, 18 SDRAM[8-9] O 2 SDRAM Byte 2 clock output
9 BUF_IN I 1 Input for 1-20 buffer
20 OE I 1 Hi-Z when LOW. Internal 100k pull-up resistor.
14 SDATA I/O 1 Data pin for I
2
C curcuitry. Internal 100k pull-up resistor.
15 SCLOCK I/O 1 Clock pin I
2
C circuitry. Internal 100k pull-up resistor.
1, 5, 10, 19, 24,
28
VDD[0-5] Power 6 3.3V power supply for SDRAM buffers
4, 8, 12, 17, 21,
25
VSS[0-5] Ground 6 Ground for SDRAM buffers
13 VDDIIC Power 1 3.3V power supply for I
2
C circuitry
16 VSSIIC Ground 1 Ground for I
2
C circuitry
OE Functionality
(1,2)
OE SDRAM[0-9]
0 Hi-Z
1 BUF_IN
I
2
C Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
11010010
Notes:
1. Used for test purposes only
2. Buffers are non-inverting
Serial Con guration Map
(1)
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit Pin Description
7 NC (Initialize to 0)
6 NC (Initialize to 0)
5 NC (Initialize to 0)
4 NC (Initialize to 0)
3 7 SDRAM3 (Active/Inactive)
2 6 SDRAM2 (Active/Inactive)
1 3 SDRAM1 (Active/Inactive)
0 2 SDRAM0 (Active/Inactive)
Note:
1. Inactive means outputs are held LOW and are disabled from
switching
08-0298
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
3
PS8165G 11/13/08
Byte1: SDRAM Active/Inactive Reg is ter
(1 = enable, 0 = disable)
Bit Pin Description
7 27 SDRAM7 (Active/Inactive)
6 26 SDRAM6 (Active/Inactive)
5 23 SDRAM5 (Active/Inactive)
4 22 SDRAM4 (Active/Inactive)
3 NC (Initialize to 0)
2 NC (Initialize to 0)
1 NC (Initialize to 0)
0 NC (Initialize to 0)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Bit Pin Description
7 18 SDRAM9 (Active/Inactive)
6 11 SDRAM8 (Active/Inactive)
5 (Reserved)
4 (Reserved)
3 (Reserved)
2 (Reserved)
1 (Reserved)
0 (Reserved)
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C182 is a slave receiver device. It can not be read back.
Sub-addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Each byte on the SDATA line must be 8-bits long (MSB rst), fol-
lowed by an acknowledge bit generated by the re ceiver.
During normal data transfers SDATA changes only when SCLOCK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SCLOCK is HIGH indicates a “stop”
condition and in di cates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ends with
a stop condition. The rst byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to ad dressed device). If the de vice’s
own address is detected, PI6C182 gen er ates an ac knowl edge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the fol low ing data bytes until another start or stop con di tion is
detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Storage Temperature ............................................................–65°C to +150°C
Ambient Temperature with Power Applied .............................–0°C to +70°C
3.3V Supply Voltage to Ground Potential ..............................–0.5V to +4.6V
DC Input Voltage ....................................................................–0.5V to +4.6V
Note:
Stresses greater than those listed under MAX I MUM RAT-
INGS may cause permanent damage to the de vice. This is
a stress rating only and functional operation of the device
at these or any other con di tions above those indicated in
the operational sec tions of this spec i ca tion is not implied.
Ex po sure to absolute maximum rating conditions for ex-
tend ed periods may affect re li abil i ty.
Maximum Ratings
Supply Current
(V
DD
= +3.465V, C
LOAD
= Max.)
Symbol Parameter Test Condidtion Min. Typ. Max. Units
I
DD
Supply Current
BUF_IN = 0 MHz 2
mA
I
DD
BUF_IN = 66.66 MHz 180
I
DD
BUF_IN = 100.00 MHz 240
I
DD
BUF_IN = 133.00 MHz 360
08-0298

PI6C182AHEX

Mfr. #:
Manufacturer:
Diodes Incorporated
Description:
Clock Buffer Precision 1 12 Clock Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet