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PI6C182AHEX

P1-P3P4-P6P7-P7
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
4
PS8165G 11/13/08
SDRAM Clock Buffer Operating Specifi cation
Symbol Parameter Test Conditions Min. Typ. Max. Units
I
OHMIN
Pull-up current V
OUT
= 2.0V -40
mA
I
OHMAX
Pull-up current V
OUT
= 3.135V -36
I
OLMIN
Pull-down current V
OUT
= 1.0V 40
I
OLMAX
Pull-down current V
OUT
= 0.4V 38
AC Timing
Symbol Parameter
66 MHz 100 MHz 125MHz
Units
Min. Max. Min. Max. Min. Max.
t
SDRISE
SDRAM CLK rise time 1.5 4.0 1.5 4.0 1.5 4.0
V/ns
t
SDFALL
SDRAM CLK fall time 1.5 4.0 1.5 4.0 1.5 4.0
t
PLH
SDRAM Buffer LH prop delay 1.0 5.5 1.0 5.5 1.0 5.5
ns
t
PHL
SDRAM Buffer HL prop delay 1.0 5.5 1.0 5.5 1.0 5.5
t
PZL
, t
PZH
SDRAM Buffer Enable delay
(1)
1.0 8.0 1.0 8.0 1.0 8.0
t
PLZ
, t
PHZ
SDRAM Buffer DIsable delay
(1)
1.0 8.0 1.0 8.0 1.0 8.0
Duty Cycle Measured at 1.5V 45 55 45 55 45 55 %
t
SDSKW
SDRAM Output-to-Output skew 250 250 200 ps
DC Operating Specifi cations (V
DD
= +3.3V ±5%, T
A
= 0°C to 70°C)
Symbol Parameter Test Conditions Min. Typ. Max. Units
V
IH
Input High voltage V
DD
2.0 V
DD
+0.3 V
V
IL
Input Low voltage V
SS
-0.3 0.8
I
IL
Input leakage current 0 < V
IN
< V
DD
-5 5 mA
V
OH
Output High voltage I
OH
= -1mA 2.4 V
V
OL
Output Low voltage I
OL
= 1mA 0.4
C
OUT
Output pin capacitance 6 pF
C
IN
Input pin capacitance 5
L
PIN
Pin Inductance 7 nH
T
A
Ambient Temperature No Airfl ow 0 70 °C
Note:
1. This Parameter specifi ed at 5MHz input frequency.
08-0298
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
5
PS8165G 11/13/08
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specifi ed
load.
2. Minimum rise/fall times are guaranteed at minimum specifi ed
load.
3. Rise/fall times are specifi ed with pure capacitive load as shown.
Testing is done with an additional 500 resistor in parallel.
Minimum and Maximum Expected
(1,2,3)
Capacitive Loads
Clock Min. Max. Units Notes
SDRAM 20 30 pF
SDRAM DIMM
Specifi caion
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specifi ed values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables
or any external connectors.
1.5V 1.5V
t
phl
t
plh
1.5V 1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
08-0298
PI6C182, PI6C182A
Precision 1-to-10 Clock Buffer
6
PS8165G 11/13/08
PCB Layout Suggestion
(1,2,3)
Notes:
1. This is only a suggested layout.
2. C1-C7 should be placed as close as possible to their respective VDD.
3. Recommended capacitor values:
C1-C7 = 0.1F, ceramic
C8 = 22F
C5
C6
C1 C7
C2
C3
C4
Ferrite Bead
VCC
C8
22uF
Via to GND Plane
Via to VDD Plane
Void in Power Plane
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VDD
VSS
VDD
VSS
VSS
VDD
VSS
Figure 2. Design Guidelines
SDRAM
R
S
10
CL
PI6C182
SDRAM
DIMM
Spec.
Clock from
Chipset
08-0298
P1-P3P4-P6P7-P7

PI6C182AHEX

Mfr. #:
Buy PI6C182AHEX
Manufacturer:
Diodes Incorporated
Description:
Clock Buffer Precision 1 12 Clock Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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