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MC33664ATL1EGR2

P1-P3P4-P6P7-P9P10-P12P13-P15
NXP Semiconductors
MC33664
Isolated network high-speed transceiver
MC33664_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Short data sheet: technical data Rev. 1.0 — 23 May 2018
7 / 15
Symbol Parameter Conditions Min Typ Max Unit
f falling edge of CSB_TX to
rising edge SCLK_TX
CSB_TX
see Figure 3 1.75 — — μs
t
RDTX_DLY
propagation delay
RDTX+
RDTX–
SCLK_TX
SCLK_TX LOW to sine
out
[1]
— 80 150 ns
g SCLK_TX LOW to CSB_TX
HIGH
see Figure 3 600 — — ns
c DATA_TX to SCLK_TX setup see Figure 3 40 — — ns
d DATA_TX hold see Figure 3 40 — — ns
t
CSB_TX_HIGH_EOM
propagation delay
CSB_TX
CSB_TX LOW to HIGH
to end of message
[1]
— — 150 ns
t
1
CSB_TX LOW period 21 μs
t
2
CSB_TX wake#up pulse
sequence timing
CSB_TX
t
1
t
2
t
1
11
00
11
00
CSB_TX HIGH period 600 μs
h time between consecutive
transmit messages
see Figure 3 1.0 3.0 — μs
Logic receive pins (CSB_RX, SCLK_RX, DATA_RX)
V
OH
HIGH-level output voltage I
OH
= −2.0 mA;
V
IO
= 3.1 V
V
IO
− 0.4 — — V
V
OL
LOW-level output voltage I
OL
= −2.0 mA;
V
IO
= 3.1 V
— — 0.4 V
f
SPI
SPI_1 frequency SCLK_RX 2.0 MHz
q pulse frequency see Figure 4 4.0 MHz
o start of message see Figure 4
[1]
500 ns
a SCLK_RX HIGH
[1]
250 ns
b SCLK_RX LOW
[1]
250 ns
NXP Semiconductors
MC33664
Isolated network high-speed transceiver
MC33664_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Short data sheet: technical data Rev. 1.0 — 23 May 2018
8 / 15
Symbol Parameter Conditions Min Typ Max Unit
t
SOM_CSB_RX
start of message to CSB_RX
CSB_RX
RDTX+
RDTX–
[1]
160 ns
t
EOM_CSB_RX
end of message to CSB_RX
CSB_RX
RDTX+
RDTX–
[1]
60 ns
t
PDB_SCLK_DATA_RX
pulse data bit to DATA_RX
and SCLK_RX
RDTX+
RDTX–
SCLK_RX
DATA_RX
[1]
280 ns
r see Figure 4
[1]
— 250 — ns
p
start of message to MSB
(receive)
p r
see Figure 4
[1]
— 600 — ns
m time between consecutive
messages received
see Figure 4 1.0 3.0 — μs
Bus differential transmitter/receiver
V
RDTX(PK_DIFF)
RDTX± differential output
voltage
R
L
= 50 Ω;
V
CC5
= 4.75 V
2.5 V
I
RDTX
RDTX± current limit sinking/sourcing to 2.5 V 65 — 300 mA
rising edge 0.74 VV
RDTX_IN(TH)
RDTX± differential receiver
threshold voltage
falling edge 0.61 0.70 V
V
RDTX_IN_HYST
RDTX± differential receiver
threshold voltage hysteresis
130 mV
V
RDTX_BIAS
transformer bias voltage transmitter in 3-state 2.5 V
f
RDTX
transmit/receive pulse
frequency
4.0 MHz
Wake-up receiver
rising edge 0.6 VV
RDTXWU_TH
RDTX± wake#up differential
receiver threshold voltage
falling edge 0.6 V
V
RDTXWU_TH_HYS
RDTX± wake#up differential
receiver threshold hysteresis
100 mV
NXP Semiconductors
MC33664
Isolated network high-speed transceiver
MC33664_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Short data sheet: technical data Rev. 1.0 — 23 May 2018
9 / 15
Symbol Parameter Conditions Min Typ Max Unit
V
RDTXWU_FLT
RDTX± wake#up filter 50 ns
[1] All bus network signals to SPI timing are referenced to 0.8 V differential threshold.
9.1 Timing diagrams
aaa-027342
MSB LSB
h
gba
d
c
fe
CSB_TX
SCLK_TX
DATA_TX
e
Figure 3. SPI transmit timing
aaa-027343
RDTX+
3.75 V
2.5 V
1.25 V
RDTX-
500 ns/bit + 2 µs
m
end of
message
bit 0
logic 0
bit 1
logic 0
bit 2
logic 1
bit 36
logic 0
bit 37
logic 0
bit 38
logic 1
start of
message
bit 39
logic 1
two pulses
positive
sine
two pulses
negative
sine
o
p
q
r
Figure 4. Transformer receive communication timing
P1-P3P4-P6P7-P9P10-P12P13-P15

MC33664ATL1EGR2

Mfr. #:
Buy MC33664ATL1EGR2
Manufacturer:
NXP / Freescale
Description:
Interface - Specialized MC33664ATL1EG/SO16///REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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