CPC5002GS Datasheet CPC5002GS | P10-P12

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4.2 Application Example

Shown below is an example of an isolated POE Controller SMBus where the SDA signal has been split into separate

SDA

and SD

OUT

signals on the isolated slave side of the barrier. In this example, the low power SMBus master, not

shown, requires a buffer (U3) capable of driving the CPC5002 input LEDs. Although selection of the appropriate

buffer is determined by the product definition and the ability to drive the LED’s, it is recommended the buffer have

Schmitt trigger inputs to ensure clean bounce-free LED drive signals. A high power SMBus master with the ability to

sink 4mA of pullup current may not require a buffer to drive the CPC5002 inputs. In this example, the POE Controllers

are specified as SMBus high power and I

C compatible. This enables the POE Controllers to drive the CPC5002

LEDs directly without the need of an external buffer.

Circuit design of the SMBus physical layer using the CPC5002 consists of two parts, one being the LED input drive

current and the other being the buffered galvanically isolated logic output signals.

The following design constraints are assumed for this example:

• Supply Voltages: V

DDx

= 3.0V to 3.6V

• Ambient Temperature: T

= 0°C to 70°C

• V

 0.4V for U3 and the POE Controllers

• I

 4mA for U3 and the POE Controllers

• Resistors:

• Tolerance = 1%

• Temperature Coefficient = 100ppm

Figure 3. Optically isolated SMBus for POE Controllers with Separate SDA

and SDA

OUT

Pins

To minimize pulse width distortion of the output signal, the input LED drive current needs to be set at the lower end of

it’s operational range. Because the forward voltage of the LED has a negative temperature coefficient this will occur at

the minimum operating temperature point with the minimum supply voltage. With V

= 3.0V and V

= 1.442V at

= 0°C and I

= 1.4mA, the calculated maximum value for the series input resistor R

is 826.8. Taking tolerance

and value change due to temperature into account, the nearest E96 standard value sets R

= 806. Using

OL_Nominal

= 0.25V and V

OL_Minimum

= 0.1V and calculating for the LED current range over the specified operating

conditions with R

= 806, the LED input current I

will be 1.455mA to 3.212mA. At nominal operating conditions with

= 25°C, the nominal LED input current is: I

F_Nominal

= 2.28mA.

SCL

SDA

INT

SCL

SDA

OUT

SMBus

POE

Controllers

CPC5002

3.3V

DDS

3.3V

DDS

3.3V

DDS

3.3V

DDS

GND

3.3V

DDM

3.3V

DDM

3.3V

DDM

CPC5002

806Ω

3.3V

DDM

3.3V

DDM

GND

3.3V

DDS

3.3V

DDS

3.3V

DDS

3.3V

DDS

0.1μF

3.3V

DDM

806Ω

R9*

R10*

INT

SCL

SDA

OUT

INT

R9 and R10 are not required for this design.

See text for explanation.

511Ω

10k

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For the outputs, the CPC5002 is compatible with both SMBus and Fast-mode I

C compatible devices. As with all

mixed type devices on a bus, the weakest driver on that bus determines the minimum value of the pullup resistor.

When the CPC5002 is the only device driving the bus as shown with U1, the minimum E96 standard value for pullup

resistors R5 and R6 will be 511. For bus loading up to 400pF, this pullup resistor value will provide for Fast-mode

compliant I

C bus speeds. At lower data rates or with less capacitive bus loading, the actual resistor value selected

can be higher.

When the CPC5002 shares a bus with another device as is the case with U2, the weakest driver sets the conditions

for selecting the correct resistor value. As stated earlier, the SMBus master is rated as a Low-power device and

therefore is only capable of sinking 350uA to an output low voltage level of 0.4V. A pullup resistor attached to the

maximum supply voltage level of 3.6V and pulled down by this low power driver limits the minimum pullup resistor

value to 9.14k. After considering tolerance and temperature effects the nearest E96 standard value is 9.31k. Most

applications will typically select the more common 10k value for R7 and R8, which allows for a 5% resistor tolerance.

Although shown but not needed in this example are pullup resistors R9 and R10. These resistors, not needed by the

CPC5002 at U2, are utilized whenever the busses they are attached to are also connected to device(s) having logic

level inputs. With heavy loading or excessive leakage on the bus the resistors provide supplementary bias to improve

pullup transition performance and to increase the output logic high level without impacting the LED input current bias

level.

The CPC5002 can be utilized to provide digital isolated buffering in a variety of unique applications. Design support is

available by contacting IXYS Integrated Circuits Division’s Applications.

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5 Manufacturing Information

5.1 Moisture Sensitivity

All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated

Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the

latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product

evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee

proper operation of our devices when handled according to the limitations and information in that standard as well as

to any limitations set forth in the information or standards referenced below.

Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced

product performance, reduction of operable life, and/or reduction of overall reliability.

This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to

the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.

5.2 ESD Sensitivity

This product is ESD Sensitive, and should be handled according to the industry standard

JESD-625.

5.3 Reflow Profile

This product has a maximum body temperature and time rating as shown below. All other guidelines of

J-STD-020 must be observed.

5.4 Board Wash

IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to

remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an

optical waveguide in many of its optically isolated products, the use of a short drying bake may be necessary if a wash

is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used.

Cleaning methods that employ ultrasonic energy should not be used.

Device Moisture Sensitivity Level (MSL) Rating

CPC5002G / CPC5002GS MSL 1

Device Maximum Temperature x Time

CPC5002G / CPC5002GS 250°C for 30 seconds

RoHS

2002/95/EC

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

CPC5002GS

Mfr. #:

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