Nexperia
74LVC8T595
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state
74LVC8T595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 9 May 2017
23 / 33
mna561
MR input
SHCP input
Q7S output
t
PHL
t
W
t
rec
V
M
V
OH
V
OL
V
I
GND
V
I
GND
V
M
V
M
Measurement points are given in Table 16.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and
the master reset to shift clock (SHCP) recovery time
001aae821
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
CC
V
M
V
OL
V
OH
GND
GND
t
PZL
t
PZH
V
M
V
M
Measurement points are given in Table 16.
V
OL
and V
OH
are typical output voltage drops that occur with the output load.
Figure 12. 3-state enable and disable times
Table 16. Measurement points
Supply voltage Input Output
V
CC(A)
, V
CC(B)
V
M
V
M
(Qn) V
M
(Q7S) V
X
V
Y
1.1 V to 1.6 V 0.5V
CC(A)
0.5V
CC(B)
0.5V
CC(A)
V
OL
+ 0.1 V V
OH
- 0.1 V
1.65 V to 2.7 V 0.5V
CC(A)
0.5V
CC(B)
0.5V
CC(A)
V
OL
+ 0.15 V V
OH
- 0.15 V
3.0 V to 5.5 V 0.5V
CC(A)
0.5V
CC(B)
0.5V
CC(A)
V
OL
+ 0.3 V V
OH
- 0.3 V
