Nexperia
74LVC8T595
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state
74LVC8T595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 9 May 2017
4 / 33
5 Pinning information
5.1 Pinning
74LVC8T595
V
CC(B)
V
CC(A)
Q0 DS
Q1 OE
Q2 STCP
Q3 SHCP
Q4 MR
Q5 Q7S
Q6 GND
Q7 GND
GND GND
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1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
MR
aaa-026287
74LVC8T595
Transparent top view
GND
Q6
Q7
GND
Q5 Q7S
Q4
Q3 SHCP
Q2 STCP
Q1 OE
Q0 DS
GND
GND
GND
(1)
V
C
C
(
B
)
V
C
C
(
A
)
9 12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
2
0
terminal 1
index area
Figure 5. Pin configuration SOT360-1 (TSSOP20)
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Figure 6. Pin configuration SOT764-1 (DHVQFN20)
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
V
CC(B)
1 supply voltage B (Qn outputs)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 3, 4, 5, 6, 7, 8, 9 data output
GND 10, 11, 12, 13 ground (0 V)
Q7S 14 serial data output
MR 15 master reset input (active LOW)
SHCP 16 shift register clock input
STCP 17 storage register clock input
OE 18 output enable input (active LOW)
DS 19 serial data input
V
CC(A)
20 supply voltage A (MR, SHCP, STCP, OE, DS inputs and Q7S
output)
Nexperia
74LVC8T595
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state
74LVC8T595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 9 May 2017
5 / 33
6 Functional description
Table 3. Function table
[1]
Supply
voltage
Input Output
V
CC(A)
, V
CC(B)
SHCP STCP OE MR DS Q7S Qn
Function
1.2 V to 5.5 V X X L L X L NC a LOW-state on MR only affects the shift
register
1.2 V to 5.5 V X L L X L L empty shift register loaded into storage
register
1.2 V to 5.5 V X X H L X L Z shift register clear; parallel outputs in high-
impedance OFF-state
1.2 V to 5.5 V X L H H Q6S NC logic HIGH-state shifted into shift register
stage 0. Contents of all shift register
stages shifted through, e.g. previous state
of stage 6 (internal Q6S) appears on the
serial output (Q7S).
1.2 V to 5.5 V X L H X NC QnS contents of shift register stages (internal
QnS) are transferred to the storage
register and parallel output stages
1.2 V to 5.5 V L H X Q6S QnS contents of shift register shifted through;
previous contents of the shift register is
transferred to the storage register and the
parallel output stages
GND
[2]
X X X X X X Z suspend mode
[1] H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
[2] When V
CC(A)
is at GND level, the device goes into suspend mode.
Nexperia
74LVC8T595
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state
74LVC8T595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 9 May 2017
6 / 33
7 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC(A)
supply voltage A -0.5 +6.5 V
V
CC(B)
supply voltage B -0.5 +6.5 V
I
IK
input clamping current V
I
< 0 V -50 - mA
V
I
input voltage
[1]
-0.5 +6.5 V
I
OK
output clamping current V
O
< 0 V -50 - mA
Active mode
[1]
[2]
[3]
-0.5 V
CCO
+ 0.5 VV
O
output voltage
Suspend or 3-state mode
[1]
-0.5 +6.5 V
I
O
output current V
O
= 0 V to V
CCO
[2]
- ±50 mA
I
CC
supply current I
CC(A)
or I
CC(B)
- 100 mA
I
GND
ground current -100 - mA
T
stg
storage temperature -65 +150 °C
P
tot
total power dissipation T
amb
= -40 °C to +125 °C
[4]
- 500 mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] V
CCO
is the supply voltage associated with the output.
[3] V
CCO
+ 0.5 V should not exceed 6.5 V
[4] For TSSOP20 package: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 package: above 60 °C the value of P
tot
derates linearly with 4.5 mW/K.
8 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
V
CC(A)
supply voltage A 1.1 5.5 V
V
CC(B)
supply voltage B 1.1 5.5 V
V
I
input voltage 0 5.5 V
Active mode
[1]
0 V
CCO
VV
O
output voltage
Suspend or 3-state mode 0 5.5 V
T
amb
ambient temperature -40 +125 °C
V
CC(A)
= 1.1 V to 1.3 V - 20 ns/V
V
CC(A)
= 1.4 V to 1.95 V - 20 ns/V
V
CC(A)
= 2.3 V to 2.7 V - 20 ns/V
V
CC(A)
= 3 V to 3.6 V - 10 ns/V
Δt/ΔV input transition rise and fall rate
V
CC(A)
= 4.5 V to 5.5 V - 5 ns/V
[1] V
CCO
is the supply voltage associated with the output.

74LVC8T595PWJ

Mfr. #:
Manufacturer:
Nexperia
Description:
74LVC8T595PW/SOT360/TSSOP20
Lifecycle:
New from this manufacturer.
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