LTC2654
17
2654f
OPERATION
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded fi rst; followed by
the 4-bit DAC address, A3-A0; and fi nally the 16-bit data
word. For the LTC2654-16 the data word comprises the
16-bit input code, ordered MSB-to-LSB. For the LTC2654-
12 the data word comprises the 12-bit input code, ordered
MSB-to-LSB followed by four don’t-care bits. Data can
only be transferred to the LTC2654 when the CS/LD signal
is low. The rising edge of CS/LD ends the data transfer
and causes the device to carry out the action specifi ed in
the 24-bit input word. The complete sequence is shown
in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The fi rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC,
n
. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16- or 12-bit input code,
and is converted to an analog voltage at the DAC output.
The update operation also powers up the selected DAC
if it had been in power-down mode. The data path and
registers are shown in the block diagram.
While the minimum input word is 24 bits, it may option-
ally be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device fi rst, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisy
chain operation, and is also available to accommodate
microprocessors that have a minimum word width of
16 bits (2 bytes). The 16-bit data word is ignored for all
commands that do not include a write operation.
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge. The SDO pin is continuously driven
and does not go high impedance when CS/LD is taken
active high.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a daisy-chain series is confi gured
by connecting SDO of each up-stream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Because of this, the devices can be addressed and con-
trolled individually by simply concatenating their input
words; the fi rst instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is fi rst taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
fi rst device as the data input. When the data transfer is
complete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111b) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four DAC outputs are needed. When in power-down,
the buffer amplifi ers, bias circuits and integrated reference
circuits are disabled, and draw essentially zero current.
The DAC outputs are put into a high-impedance state, and
the output pins are passively pulled to ground through
individual 80k resistors. Input- and DAC-register contents
are not disturbed during power-down.
