LTC2654BIGN-L16#TRPBF Datasheet LTC2654BCGN-H16#PBF, LTC2654IGN-H12#PBF, LTC2654BIGN-L16#PBF | P19-P21

LTC2654

2654f

OPERATION

Any channel or combination of DAC channels can be put

into power-down mode by using command 0100b in

combination with the appropriate DAC address, (

). The

integrated reference is automatically powered down when

external reference is selected using command 0111b. In

addition, all the DAC channels and the integrated refer-

ence together can be put into power-down mode using

Power-Down Chip command 0101b. For all power-down

commands the 16-bit data word is ignored, but still needs

to be clocked in.

Normal operation resumes by executing any command

which includes a DAC update, in software as shown in

Table 1 or by taking the asynchronous LDAC pin low.

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state is

powered up and updated, normal settling is delayed. If less

than four DACs are in a powered-down state prior to the

update command, the power-up delay time is 12s. If on

the other hand, all four DACs and the integrated reference

are powered down, then the main bias generation circuit

block has been automatically shut down in addition to the

individual DAC ampliﬁ ers and integrated reference. In this

case, the power up delay time is 14s. The power-up of

integrated reference depends on the command that pow-

ered it down. If the reference is powered down using the

Select External Reference Command (0111b) then it can

only be powered back-up using Select Internal Reference

Command (0110b). However if the reference was powered

down using Power-Down Chip Command (0101b) then in

addition to Select Internal Reference Command (0110b),

any command that powers up the DACs will also power-up

the integrated reference.

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 1, the

LDAC pin asynchronously updates all the DAC registers

with the contents of the input registers.

If CS/LD is high, a low on the LDAC pin causes all the

DAC registers to be updated with the contents of the in-

put registers.

If CS/LD is low, a low going pulse on the LDAC pin before

the rising edge of CS/LD powers up all the DAC outputs but

does not cause the output to be updated. If LDAC remains

low after the rising edge of CS/LD, then LDAC is recognized,

the command speciﬁ ed in the 24-bit word just transferred

is executed and the DAC outputs are updated.

The DAC outputs are powered up when LDAC is taken

low, independent of the state of CS/LD. The integrated

reference is also powered up if it was powered down us-

ing Power-Down Chip (0101b) command. The integrated

reference will not power up when LDAC is taken low, if

it was powered down using Select External Reference

(0111b) Command.

If LDAC is low at the time CS/LD goes high, it inhibits any

software power-down command (Power-Down

, Power-

Down Chip, Select External Reference) that was speciﬁ ed

in the input word.

Reference Modes

For applications where an accurate external reference is

not available, the LTC2654 has a user-selectable, inte-

grated reference. The LTC2654-L has a 1.25V reference

that provides a full-scale output of 2.5V. The LTC2654-H

has a 2.048V reference that provides a full-scale output

of 4.096V. Both references exhibit a typical temperature

drift of 2ppm/°C. Internal reference mode can be selected

by using command 0110b, and is the power-on default.

A buffer is needed if the internal reference is required to

drive external circuitry. For reference stability and low

noise, connect a 0.1µF capacitor between REFCOMP and

GND. In this conﬁ guration, the internal reference can drive

up to 0.1µF capacitive load without any stability problems.

In order to ensure stable operation, the capacitive load on

REFIN/OUT pin should not exceed the capacitive load on

the REFCOMP pin.

The DAC can also operate in external reference mode using

command 0111b. In this mode, REFIN/OUT pin acts as an

input that sets the DAC’s reference voltage. The input is

high impedance and does not load the external reference

source. The acceptable voltage range at this pin is 0.5V ≤

REFIN/OUT ≤ V

/2. The resulting full-scale output voltage

is 2•V

REFIN/OUT

. For using External Reference at start-up,

see the Power Supply Sequencing and Start-Up Section.

LTC2654

2654f

OPERATION

Integrated Reference Buffers

Each of the four DACs in the LTC2654 has its own inte-

grated high performance reference buffer. The buffers have

very high input impedance and do not load the reference

voltage source. These buffers shield the reference voltage

from glitches caused by DAC switching and thus minimize

DAC-to-DAC Dynamic Crosstalk. Typically DAC-to-DAC

crosstalk is less than 3nV•s. By tying 0.22µF capacitors

between REFCOMP and GND, and also between REFIN/

OUT and GND, this number can be reduced to less than

1nV•s. See the curve DAC-to-DAC Dynamic Crosstalk in

the Typical Performance Characteristics section.

Voltage Outputs

Each of the LTC2654’s four rail-to-rail output ampliﬁ ers con-

tained in these parts has guaranteed load regulation when

sourcing or sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the ampliﬁ er’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is expressed

in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The ampliﬁ ers’ DC output

impedance is 0.04 when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 30 typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =

30 • 1mA = 30mV. See the graph Headroom at Rails vs

Output Current in the Typical Performance Characteristics

section.

The ampliﬁ ers are stable driving capacitive loads of up

to 1000pF.

Board Layout

The excellent load regulation and DC crosstalk performance

of these devices is achieved in part by keeping signal and

power grounds separate.

The PC board should have separate areas for the analog

and digital sections of the circuit. This keeps digital signals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continuous

and uninterrupted plane, except for necessary lead pads

and vias, with signal traces on another layer.

The GND pin functions as a return path for power supply

currents in the device and should be connected to analog

ground. The REFLO pin should be connected to system

star ground. Resistance from the REFLO pin to system

star ground should be as low as possible.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited

to voltages within the supply range.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 3b. Similarly, limiting can occur in external refer-

ence mode near full-scale when the REFIN/OUT pin is at

/2. If V

REFIN/OUT

= V

/2 and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits

at V

as shown in Figure 3c. No full-scale limiting can

occur if V

REFIN/OUT

≤ (V

– FSE)/2.

Offset and linearity are deﬁ ned and tested over the region

of the DAC transfer function where no output limiting can

occur.

LTC2654

2654f

OPERATION

Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of

Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

2654 F04

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

32,7680 4,095

INPUT CODE

OUTPUT

VOLTAGE

(a)

REF

= V

REF

= V

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

LTC2654BIGN-L16#TRPBF

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 16-Bit SPI Quad DAC (1.25V Reference, 4LSB INL)

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