RX5500 Datasheet RX5500 | P4-P6

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ASH Receiver Block Diagram & Timing Cycle

Antenna

Pulse

Generator

SAW

Delay Line

SAW Filter RFA1 RFA2

Data

Out

Detector &

Low-Pass

Filter

RF Data Pulse

P1 P2

RFA1 Out

RF Input

Delay Line

Out

PW2

PW1

PRI

PRC

Figure 1

ASH Receiver Theory of Operation

Introduction

Murata’s RX5500 series amplifier-sequenced hybrid (ASH)

receivers are specifically designed for short-range wireless control

and data communication applications. The receivers provide

robust operation, very small size, low power consumption and low

implementation cost. All critical RF functions are contained in the

hybrid, simplifying and speeding design-in. The ASH receiver can

be readily configured to support a wide range of data rates and

protocol requirements. The receiver features virtually no RF

emissions, making it easy to certify to short-range (unlicensed)

radio regulations.

Amplifier-Sequenced Receiver Operation

The ASH receiver’s unique feature set is made possible by its

system architecture. The heart of the receiver is the amplifier-

sequenced receiver section, which provides more than 100 dB of

stable RF and detector gain without any special shielding or

decoupling provisions. Stability is achieved by distributing the total

RF gain over time. This is in contrast to a superheterodyne

receiver, which achieves stability by distributing total RF gain over

multiple frequencies.

Figure 1 shows the basic block diagram and timing cycle for an

amplifier-sequenced receiver. Note that the bias to RF amplifiers

RFA1 and RFA2 are independently controlled by a pulse

generator, and that the two amplifiers are coupled by a surface

acoustic wave (SAW) delay line, which has a typical delay of

0.5 µs.

An incoming RF signal is first filtered by a narrow-band SAW filter,

and is then applied to RFA1. The pulse generator turns RFA1 ON

for 0.5 µs. The amplified signal from RFA1 emerges from the SAW

delay line at the input to RFA2. RFA1 is now switched OFF and

RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.

The ON time for RFA2 is usually set at 1.1 times the ON time for

RFA1, as the filtering effect of the SAW delay line stretches the

signal pulse from RFA1 somewhat. As shown in the timing

diagram, RFA1 and RFA2 are never on at the same time, assuring

excellent receiver stability. Note that the narrow-band SAW filter

eliminates sampling sideband responses outside of the receiver

passband, and the SAW filter and delay line act together to provide

very high receiver ultimate rejection.

Amplifier-sequenced receiver operation has several interesting

characteristics that can be exploited in system design. The RF

amplifiers in an amplifier-sequenced receiver can be turned on and

off almost instantly, allowing for very quick power-down (sleep)

and wake-up times. Also, both RF amplifiers can be off between

ON sequences to trade-off receiver noise figure for lower average

current consumption. The effect on noise figure can be modeled as

if RFA1 is on continuously, with an attenuator placed in front of it

with a loss equivalent to 10*log

(RFA1 duty factor), where the

duty factor is the average amount of time RFA1 is ON (up to 50%).

RX5500 (R) 4/15/15 Page 5 of 9

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Figure 2

Since an amplifier-sequenced receiver is inherently a sampling

receiver, the overall cycle time between the start of one RFA1 ON

sequence and the start of the next RFA1 ON sequence should be

set to sample the narrowest RF data pulse at least 10 times.

Otherwise, significant edge jitter will be added to the detected data

pulse.

RX5500 Series ASH Receiver Block Diagram

Figure 2 is the general block diagram of the RX5500 series ASH

receiver. Please refer to Figure 2 for the following discussions.

Antenna Port

The only external RF components needed for the receiver are the

antenna and its matching components. Antennas presenting an

impedance in the range of 35 to 72 ohms resistive can be

satisfactorily matched to the RFIO pin with a series matching coil

and a shunt matching/ESD protection coil. Other antenna

impedances can be matched using two or three components. For

some impedances, two inductors and a capacitor will be required.

A DC path from RFIO to ground is required for ESD protection.

Receiver Chain

The output of the SAW filter drives amplifier RFA1. The output of

RFA1 drives the SAW delay line, which has a nominal delay of 0.5

µs.

The second amplifier, RFA2, provides 51 dB of gain below

saturation. The output of RFA2 drives a full-wave detector with 19

dB of threshold gain. The onset of saturation in each section of

RFA2 is detected and summed to provide a logarithmic response.

This is added to the output of the full-wave detector to produce an

overall detector response that is square law for low signal levels,

and transitions into a log response for high signal levels. This

combination provides excellent threshold sensitivity and more than

70 dB of detector dynamic range. In combination with the 30 dB of

AGC range in RFA1, more than 100 dB of receiver dynamic range

is achieved.

The detector output drives a gyrator filter. The filter provides a

three-pole, 0.05 degree equiripple low-pass response with

excellent group delay flatness and minimal pulse ringing. The 3 dB

bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an

external resistor.

The filter is followed by a base-band amplifier which boosts the

detected signal to the BBOUT pin. When the receiver RF amplifiers

are operating at a 50%-50% duty cycle, the BBOUT signal

changes about 10 mV/dB, with a peak-to-peak signal level of up to

685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak

signal level are proportionately less. The detected signal is riding

on a 1.1 Vdc level that varies somewhat with supply voltage,

temperature, etc. BBOUT is coupled to the CMPIN pin or to an

external data recovery process (DSP, etc.) by a series capacitor.

The correct value of the series capacitor depends on data rate,

data run length, and other factors as discussed in the ASH

Transceiver Designer’s Guide.

When the receiver is placed in the power-down (sleep) mode, the

output impedance of BBOUT becomes very high. This feature

helps preserve the charge on the coupling capacitor to minimize

data slicer stabilization time when the receiver switches out of the

sleep mode.

Data Slicers

The CMPIN pin drives data slicer DS1, which convert the analog

signal from BBOUT back into a digital stream. Data slicer DS1 is a

capacitively-coupled comparator with provisions for an adjustable

threshold. The threshold, or squelch, offsets the comparator’s

RX5500 Series ASH Receiver Block Diagram

RFA1 RFA2

SAW

Delay Line

SAW

CR Filter

Log

Antenna

RFIO

ESD

Choke

Detector

Low-Pass

Filter

Pulse Generator

& RF Amp Bias

LPFADJ

PRATE PWIDTH

RXDATA

CNTRL1 CNTRL0

REF

THLD1

Bias Control

Power

Down

Control

Threshold

Control

BBOUT

DS1

Ref Thld

BBO

LPF

TH1

17 18

VCC1: Pin 2

VCC2: Pin 16

GND1: Pin 1

GND2: Pin 10

GND3: Pin 19

NC: Pin 8

RREF: Pin 11

CMPIN: Pin 6

NC: Pin 4

NC: Pin 12

RFA1

11 RREF

RX5500 (R) 4/15/15 Page 6 of 9

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slicing level from 0 to 90 mV, and is set with a resistor between the

RREF and THLD1 pins. This threshold allows a trade-off between

receiver sensitivity and output noise density in the no-signal

condition. For best sensitivity, the threshold is set to 0. In this case,

noise is output continuously when no signal is present. This, in

turn, requires the circuit being driven by the RXDATA pin to be able

to process noise (and signals) continuously.

This can be a problem if RXDATA is driving a circuit that must

“sleep” when data is not present to conserve power, or when it its

necessary to minimize false interrupts to a multitasking processor.

In this case, noise can be greatly reduced by increasing the

threshold level, but at the expense of sensitivity. The best 3 dB

bandwidth for the low-pass filter is also affected by the threshold

level setting of DS1. The bandwidth must be increased as the

threshold is increased to minimize data pulse-width variations with

signal amplitude.

Receiver Pulse Generator and RF Amplifier Bias

The receiver amplifier-sequence operation is controlled by the

Pulse Generator & RF Amplifier Bias module, which in turn is

controlled by the PRATE and PWIDTH input pins, and the Power

Down (sleep) Control Signal from the Bias Control function.

In the low data rate mode, the interval between the falling edge of

one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse

tPRI is set by a resistor between the PRATE pin and ground. The

interval can be adjusted between 0.1 and 5 µs. In the high data rate

mode (selected at the PWIDTH pin) the receiver RF amplifiers

operate at a nominal 50%-50% duty cycle. In this case, the start-

to-start period tPRC for ON pulses to RFA1 are controlled by the

PRATE resistor over a range of 0.1 to 1.1 µs.

In the low data rate mode, the PWIDTH pin sets the width of the

ON pulse t

PW1

to RFA1 with a resistor to ground (the ON pulse

width t

PW2

to RFA2 is set at 1.1 times the pulse width to RFA1 in

the low data rate mode). The ON pulse width t

PW1

can be adjusted

between 0.55 and 1 µs. However, when the PWIDTH pin is

connected to Vcc through a 1 M resistor, the RF amplifiers operate

at a nominal 50%-50% duty cycle, facilitating high data rate

operation. In this case, the RF amplifiers are controlled by the

PRATE resistor as described above.

Both receiver RF amplifiers are turned off by the Power Down

Control Signal, which is invoked in the sleep mode.

Receiver Mode Control

The receiver operating modes – receive and power-down (sleep),

are controlled by the Bias Control function, and are selected with

the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and

CNTRL0 both high place the unit in the receive mode. Setting

CNTRL1 and CNTRL0 both low place the unit in the power-down

(sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible

inputs. These inputs must be held at a logic level; they cannot be

left unconnected.

Receiver Event Timing

Receiver event timing is summarized in Table 1. Please refer to

this table for the following discussions.

Turn-On Timing

The maximum time t

required for the receive function to become

operational at turn on is influenced by two factors. All receiver

circuitry will be operational 5 ms after the supply voltage reaches

2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC

stabilized in 3 time constants (3*

tBBC

). The total turn-on time to

stable receiver operation for a 10 ms power supply rise time is:

= 15 ms + 3*t

BBC

Sleep and Wake-Up Timing

The maximum transition time from the receive mode to the power-

down (sleep) mode t

is 10 µs after CNTRL1 and CNTRL0 are

both low (1 µs fall time).

The maximum transition time t

from the sleep mode to the

receive mode is 3*t

BBC

, where t

BBC

is the BBOUT-CMPIN

coupling-capacitor time constant. When the operating temperature

is limited to 60 °C, the time required to switch from sleep to receive

is dramatically less for short sleep times, as less charge leaks

away from the BBOUT- CMPIN coupling capacitor.

Pulse Generator Timing

In the low data rate mode, the interval t

PRI

between the falling edge

of an ON pulse to the first RF amplifier and the rising edge of the

next ON pulse to the first RF amplifier is set by a resistor R

between the PRATE pin and ground. The interval can be adjusted

between 0.1 and 5 µs with a resistor in the range of 51 K to 2000

K. The value of the R

is given by:

= 404* t

PRI

+ 10.5, where t

PRI

is in µs, and R

is in kilohms

In the high data rate mode (selected at the PWIDTH pin) the

receiver RF amplifiers operate at a nominal 50%-50% duty cycle.

In this case, the period t

PRC

from the start of an ON pulse to the

first RF amplifier to the start of the next ON pulse to the first RF

amplifier is controlled by the PRATE resistor over a range of 0.1 to

1.1 µs using a resistor of 11 K to 220 K. In this case R

is given

by:

= 198* t

PRC

- 8.51, where t

PRC

is in µs and R

is in kilohms

In the low data rate mode, the PWIDTH pin sets the width of the

ON pulse to the first RF amplifier t

PW1

with a resistor R

ground (the ON pulse width to the second RF amplifier t

PW2

is set

at 1.1 times the pulse width to the first RF amplifier in the low data

rate mode). The ON pulse width t

PW1

can be adjusted between

0.55 and 1 µs with a resistor value in the range of 200 K to 390 K.

The value of R

is given by:

= 404* t

PW1

- 18.6, where t

PW1

is in µs and R

is in kilohms

However, when the PWIDTH pin is connected to Vcc through a 1

M resistor, the RF amplifiers operate at a nominal 50%-50% duty

cycle, facilitating high data rate operation. In this case, the RF

amplifiers are controlled by the PRATE resistor as described

above.

LPF Group Delay

The low-pass filter group delay is a function of the filter 3 dB

bandwidth, which is set by a resistor R

LPF

to ground at the LPFADJ

pin. The minimum 3 dB bandwidth f

LPF

= 1445/R

LPF

, where f

LPF

in kHz, and R

LPF

is in kilohms.

The maximum group delay t

FGD

= 1750/f

LPF

= 1.21*R

LPF

, where

FGD

is in µs, f

LPF

in kHz, and R

LPF

in kilohms.

P1-P3 P4-P6 P7-P9

RX5500

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RF Receiver 2G ASH Receiver 433.92 MHZ 19.2kbps

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